activity
20242026
most citedThe Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Models

21 citations · 25 across the 18 of their papers we have counts for

collaborators

18 papers

cs.LG2026

UniRTL: Unifying Code and Graph for Robust RTL Representation Learning

Yi Liu, Hongji Zhang, Lei Chen +2

Developing effective representations for register transfer level (RTL) designs is crucial for accelerating the hardware design workflow. Existing approaches, however, typically rel…

cs.LG2026

Context Distillation as Latent Memory Management

Ziyang Zheng, Zeju Li, Xiangyu Wen +5

Context distillation compresses contextual information into model parameters, yet existing methods often ignore how multiple distilled latent memories should be stored, retrieved,…

cs.NE2026

Kernel Foundry: A Diagnosis-driven Evolutionary Kernel Optimizer with Multi-Experts

Zixuan Huang, Da Chen, Kecheng Huang +5

Generating high-performance GPU kernels remains challenging due to the need for both correctness and hardware-aware optimization. While large language models (LLMs) show promise in…

cs.AR2025

SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding

Chengxi Li, Yang Sun, Lei Chen +3

This paper proposes smaRTLy: a new optimization technique for multiplexers in Register-Transfer Level (RTL) logic synthesis. Multiplexer trees are very common in RTL designs, and t…

cs.LG2025

ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring

Dimitris Tsaras, Xing Li, Lei Chen +2

In electronic design automation, logic optimization operators play a crucial role in minimizing the gate count of logic circuits. However, their computation demands are high. Opera…

cs.LG2025

Beyond Tokens: Enhancing RTL Quality Estimation via Structural Graph Learning

Yi Liu, Hongji Zhang, Yiwen Wang +4

Estimating the quality of register transfer level (RTL) designs is crucial in the electronic design automation (EDA) workflow, as it enables instant feedback on key performance met…

cs.CL2025

LoopServe: An Adaptive Dual-phase LLM Inference Acceleration System for Multi-Turn Dialogues

Haoyang Li, Zhanchao Xu, Yiming Li +9

Multi-turn dialogues are essential in many real-world applications of large language models, such as chatbots and virtual assistants. As conversation histories become longer, exist…

cs.LG2025

SpaceGNN: Multi-Space Graph Neural Network for Node Anomaly Detection with Extremely Limited Labels

Xiangyu Dong, Xingyi Zhang, Lei Chen +2

Node Anomaly Detection (NAD) has gained significant attention in the deep learning community due to its diverse applications in real-world scenarios. Existing NAD methods primarily…

cs.LG2024

MTLSO: A Multi-Task Learning Approach for Logic Synthesis Optimization

Faezeh Faez, Raika Karimi, Yingxue Zhang +4

Electronic Design Automation (EDA) is essential for IC design and has recently benefited from AI-based techniques to improve efficiency. Logic synthesis, a key EDA stage, transform…

cs.LG2024

SeaDAG: Semi-autoregressive Diffusion for Conditional Directed Acyclic Graph Generation

Xinyi Zhou, Xing Li, Yingzhao Lian +6

We introduce SeaDAG, a semi-autoregressive diffusion model for conditional generation of Directed Acyclic Graphs (DAGs). Considering their inherent layer-wise structure, we simulat…

cs.LG2024

ShortCircuit: AlphaZero-Driven Circuit Design

Dimitrios Tsaras, Antoine Grosnit, Lei Chen +3

Chip design relies heavily on generating Boolean circuits, such as AND-Inverter Graphs (AIGs), from functional descriptions like truth tables. This generation operation is a key pr…

cs.AR2024★ 1 cited

RTLRewriter: Methodologies for Large Models aided RTL Code Optimization

Xufeng Yao, Yiwen Wang, Xing Li +6

Register Transfer Level (RTL) code optimization is crucial for enhancing the efficiency and performance of digital circuits during early synthesis stages. Currently, optimization r…

cs.AI2024

Logic Synthesis Optimization with Predictive Self-Supervision via Causal Transformers

Raika Karimi, Faezeh Faez, Yingxue Zhang +4

Contemporary hardware design benefits from the abstraction provided by high-level logic gates, streamlining the implementation of logic circuits. Logic Synthesis Optimization (LSO)…

cs.LO2024

Logic Synthesis with Generative Deep Neural Networks

Xihan Li, Xing Li, Lei Chen +3

While deep learning has achieved significant success in various domains, its application to logic circuit design has been limited due to complex constraints and strict feasibility…

cs.LG2024★ 2 cited

SmoothGNN: Smoothing-aware GNN for Unsupervised Node Anomaly Detection

Xiangyu Dong, Xingyi Zhang, Yanni Sun +3

The smoothing issue in graph learning leads to indistinguishable node representations, posing significant challenges for graph-related tasks. However, our experiments reveal that t…

cs.AR2024★ 21 cited

The Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Models

Lei Chen, Yiqi Chen, Zhufei Chu +36

Within the Electronic Design Automation (EDA) domain, AI-driven solutions have emerged as formidable tools, yet they typically augment rather than redefine existing methodologies.…

cs.LG2024

PreRoutGNN for Timing Prediction with Order Preserving Partition: Global Circuit Pre-training, Local Delay Learning and Attentional Cell Modeling

Ruizhe Zhong, Junjie Ye, Zhentao Tang +4

Pre-routing timing prediction has been recently studied for evaluating the quality of a candidate cell placement in chip design. It involves directly estimating the timing metrics…

cs.LG2024★ 1 cited

Circuit Transformer: A Transformer That Preserves Logical Equivalence

Xihan Li, Xing Li, Lei Chen +3

Implementing Boolean functions with circuits consisting of logic gates is fundamental in digital computer design. However, the implemented circuit must be exactly equivalent, which…