20 citations · 103 across the 26 of their papers we have counts for
28 papers
Code for All: Educational Applications of the "Vibe Coding" Hackathon in Programming Education across All Skill Levels
Ashley J. Chen, Yijia Cao, Minghao Shao +2
The emergence of large language models has enabled vibe coding, a natural language approach to programming in which users describe intent and AI generates or revises code, potentia…
VeriInteresting: An Empirical Study of Model Prompt Interactions in Verilog Code Generation
Luca Collini, Andrew Hennesee, Patrick Yubeaton +2
Rapid advances in language models (LMs) have created new opportunities for automated code generation while complicating trade-offs between model characteristics and prompt design c…
GUIDE: GenAI Units In Digital Design Education
Weihua Xiao, Jason Blocklove, Matthew DeLorenzo +6
GenAI Units In Digital Design Education (GUIDE) is an open courseware repository with runnable Google Colab labs and other materials. We describe the repository's architecture and…
GroundCount: Grounding Vision-Language Models with Object Detection for Mitigating Counting Hallucinations
Boyuan Chen, Minghao Shao, Siddharth Garg +2
Vision Language Models (VLMs) exhibit persistent hallucinations in counting tasks, with accuracy substantially lower than other visual reasoning tasks (excluding sentiment). This p…
Hybrid-NL2SVA: Integrating RAG and Finetuning for LLM-based NL2SVA
Weihua Xiao, Derek Ekberg, Siddharth Garg +1
SystemVerilog Assertions (SVAs) are critical for verifying the correctness of hardware designs, but manually writing them from natural language property descriptions, i.e., NL2SVA,…
ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction
Luca Collini, Jitendra Bhandari, Chiara Muscari Tomajoli +6
In the modern global Integrated Circuit (IC) supply chain, protecting intellectual property (IP) is a complex challenge, and balancing IP loss risk and added cost for theft counter…
VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification
Patrick Yubeaton, Andre Nakkab, Weihua Xiao +4
This paper introduces VeriThoughts, a novel dataset designed for reasoning-based Verilog code generation. We establish a new benchmark framework grounded in formal verification met…
MARVEL: Multi-Agent RTL Vulnerability Extraction using Large Language Models
Luca Collini, Baleegh Ahmad, Joey Ah-kiow +1
Hardware security verification is a challenging and time-consuming task. Design engineers may use formal verification, linting, and functional simulation tests, coupled with analys…
LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs
Baleegh Ahmad, Hammond Pearce, Ramesh Karri +1
While static analysis is useful in detecting early-stage hardware security bugs, its efficacy is limited because it requires information to form checks and is often unable to expla…
Can Reasoning Models Reason about Hardware? An Agentic HLS Perspective
Luca Collini, Andrew Hennessee, Ramesh Karri +1
Recent Large Language Models (LLMs) such as OpenAI o3-mini and DeepSeek-R1 use enhanced reasoning through Chain-of-Thought (CoT). Their potential in hardware design, which relies o…
Need for zkSpeed: Accelerating HyperPlonk for Zero-Knowledge Proofs
Alhad Daftardar, Jianqiao Mo, Joey Ah-kiow +4
Zero-Knowledge Proofs (ZKPs) are rapidly gaining importance in privacy-preserving and verifiable computing. ZKPs enable a proving party to prove the truth of a statement to a verif…
The Impact of Logic Locking on Confidentiality: An Automated Evaluation
Lennart M. Reimann, Evgenii Rezunov, Dominik Germek +4
Logic locking secures hardware designs in untrusted foundries by incorporating key-driven gates to obscure the original blueprint. While this method safeguards the integrated circu…
PrefixLLM: LLM-aided Prefix Circuit Design
Weihua Xiao, Venkata Sai Charan Putrevu, Raghu Vamshi Hemadri +2
Prefix circuits are fundamental components in digital adders, widely used in digital systems due to their efficiency in calculating carry signals. Synthesizing prefix circuits with…
C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap
Luca Collini, Siddharth Garg, Ramesh Karri
High-Level Synthesis (HLS) tools offer rapid hardware design from C code, but their compatibility is limited by code constructs. This paper investigates Large Language Models (LLMs…
Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI
Jitendra Bhandari, Vineet Bhat, Yuheng He +3
Masala-CHAI is a fully automated framework leveraging large language models (LLMs) to generate Simulation Programs with Integrated Circuit Emphasis (SPICE) netlists. It addresses a…
Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback
Jason Blocklove, Shailja Thakur, Benjamin Tan +3
Traditionally, digital hardware designs are written in the Verilog hardware description language (HDL) and debugged manually by engineers. This can be time-consuming and error-pron…
Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design
Andre Nakkab, Sai Qian Zhang, Ramesh Karri +1
Large Language Models (LLMs) are effective in computer hardware synthesis via hardware description language (HDL) generation. However, LLM-assisted approaches for HDL generation st…
C2HLSC: Can LLMs Bridge the Software-to-Hardware Design Gap?
Luca Collini, Siddharth Garg, Ramesh Karri
High Level Synthesis (HLS) tools offer rapid hardware design from C code, but their compatibility is limited by code constructs. This paper investigates Large Language Models (LLMs…
LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines
Jitendra Bhandari, Johann Knechtel, Ramesh Narayanaswamy +2
This work investigates the potential of tailoring Large Language Models (LLMs), specifically GPT3.5 and GPT4, for the domain of chip testing. A key aspect of chip design is functio…
Evaluating LLMs for Hardware Design and Test
Jason Blocklove, Siddharth Garg, Ramesh Karri +1
Large Language Models (LLMs) have demonstrated capabilities for producing code in Hardware Description Languages (HDLs). However, most of the focus remains on their abilities to wr…
An Empirical Evaluation of LLMs for Solving Offensive Security Challenges
Minghao Shao, Boyuan Chen, Sofija Jancheska +4
Capture The Flag (CTF) challenges are puzzles related to computer security scenarios. With the advent of large language models (LLMs), more and more CTF participants are using LLMs…
Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS
Matthew DeLorenzo, Animesh Basak Chowdhury, Vasudev Gohil +4
Existing large language models (LLMs) for register transfer level code generation face challenges like compilation failures and suboptimal power, performance, and area (PPA) effici…
ChIRAAG: ChatGPT Informed Rapid and Automated Assertion Generation
Bhabesh Mali, Karthik Maddala, Vatsal Gupta +3
System Verilog Assertion (SVA) formulation -- a critical yet complex task is a prerequisite in the Assertion Based Verification (ABV) process. Traditionally, SVA formulation involv…
Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization
Animesh Basak Chowdhury, Marco Romanelli, Benjamin Tan +2
Logic synthesis, a pivotal stage in chip design, entails optimizing chip specifications encoded in hardware description languages like Verilog into highly efficient implementations…