20 citations · 103 across the 26 of their papers we have counts for
12 papers · 1 filter
PrefixLLM: LLM-aided Prefix Circuit Design
Weihua Xiao, Venkata Sai Charan Putrevu, Raghu Vamshi Hemadri +2
Prefix circuits are fundamental components in digital adders, widely used in digital systems due to their efficiency in calculating carry signals. Synthesizing prefix circuits with…
C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap
Luca Collini, Siddharth Garg, Ramesh Karri
High-Level Synthesis (HLS) tools offer rapid hardware design from C code, but their compatibility is limited by code constructs. This paper investigates Large Language Models (LLMs…
Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI
Jitendra Bhandari, Vineet Bhat, Yuheng He +3
Masala-CHAI is a fully automated framework leveraging large language models (LLMs) to generate Simulation Programs with Integrated Circuit Emphasis (SPICE) netlists. It addresses a…
Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback
Jason Blocklove, Shailja Thakur, Benjamin Tan +3
Traditionally, digital hardware designs are written in the Verilog hardware description language (HDL) and debugged manually by engineers. This can be time-consuming and error-pron…
Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design
Andre Nakkab, Sai Qian Zhang, Ramesh Karri +1
Large Language Models (LLMs) are effective in computer hardware synthesis via hardware description language (HDL) generation. However, LLM-assisted approaches for HDL generation st…
C2HLSC: Can LLMs Bridge the Software-to-Hardware Design Gap?
Luca Collini, Siddharth Garg, Ramesh Karri
High Level Synthesis (HLS) tools offer rapid hardware design from C code, but their compatibility is limited by code constructs. This paper investigates Large Language Models (LLMs…
LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines
Jitendra Bhandari, Johann Knechtel, Ramesh Narayanaswamy +2
This work investigates the potential of tailoring Large Language Models (LLMs), specifically GPT3.5 and GPT4, for the domain of chip testing. A key aspect of chip design is functio…
Evaluating LLMs for Hardware Design and Test
Jason Blocklove, Siddharth Garg, Ramesh Karri +1
Large Language Models (LLMs) have demonstrated capabilities for producing code in Hardware Description Languages (HDLs). However, most of the focus remains on their abilities to wr…
An Empirical Evaluation of LLMs for Solving Offensive Security Challenges
Minghao Shao, Boyuan Chen, Sofija Jancheska +4
Capture The Flag (CTF) challenges are puzzles related to computer security scenarios. With the advent of large language models (LLMs), more and more CTF participants are using LLMs…
Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS
Matthew DeLorenzo, Animesh Basak Chowdhury, Vasudev Gohil +4
Existing large language models (LLMs) for register transfer level code generation face challenges like compilation failures and suboptimal power, performance, and area (PPA) effici…
ChIRAAG: ChatGPT Informed Rapid and Automated Assertion Generation
Bhabesh Mali, Karthik Maddala, Vatsal Gupta +3
System Verilog Assertion (SVA) formulation -- a critical yet complex task is a prerequisite in the Assertion Based Verification (ABV) process. Traditionally, SVA formulation involv…
Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization
Animesh Basak Chowdhury, Marco Romanelli, Benjamin Tan +2
Logic synthesis, a pivotal stage in chip design, entails optimizing chip specifications encoded in hardware description languages like Verilog into highly efficient implementations…