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20222026
most citedAutoChip: Automating HDL Generation Using LLM Feedback

20 citations · 103 across the 26 of their papers we have counts for

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Showing 2025Show all

8 papers · 1 filter

cs.CL2025

Hybrid-NL2SVA: Integrating RAG and Finetuning for LLM-based NL2SVA

Weihua Xiao, Derek Ekberg, Siddharth Garg +1

SystemVerilog Assertions (SVAs) are critical for verifying the correctness of hardware designs, but manually writing them from natural language property descriptions, i.e., NL2SVA,…

cs.CR2025★ 3 cited

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction

Luca Collini, Jitendra Bhandari, Chiara Muscari Tomajoli +6

In the modern global Integrated Circuit (IC) supply chain, protecting intellectual property (IP) is a complex challenge, and balancing IP loss risk and added cost for theft counter…

cs.PL2025

VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification

Patrick Yubeaton, Andre Nakkab, Weihua Xiao +4

This paper introduces VeriThoughts, a novel dataset designed for reasoning-based Verilog code generation. We establish a new benchmark framework grounded in formal verification met…

cs.CR2025

MARVEL: Multi-Agent RTL Vulnerability Extraction using Large Language Models

Luca Collini, Baleegh Ahmad, Joey Ah-kiow +1

Hardware security verification is a challenging and time-consuming task. Design engineers may use formal verification, linting, and functional simulation tests, coupled with analys…

cs.CR2025

LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs

Baleegh Ahmad, Hammond Pearce, Ramesh Karri +1

While static analysis is useful in detecting early-stage hardware security bugs, its efficacy is limited because it requires information to form checks and is often unable to expla…

cs.AI2025

Can Reasoning Models Reason about Hardware? An Agentic HLS Perspective

Luca Collini, Andrew Hennessee, Ramesh Karri +1

Recent Large Language Models (LLMs) such as OpenAI o3-mini and DeepSeek-R1 use enhanced reasoning through Chain-of-Thought (CoT). Their potential in hardware design, which relies o…

cs.AR2025★ 12 cited

Need for zkSpeed: Accelerating HyperPlonk for Zero-Knowledge Proofs

Alhad Daftardar, Jianqiao Mo, Joey Ah-kiow +4

Zero-Knowledge Proofs (ZKPs) are rapidly gaining importance in privacy-preserving and verifiable computing. ZKPs enable a proving party to prove the truth of a statement to a verif…

cs.CR2025★ 1 cited

The Impact of Logic Locking on Confidentiality: An Automated Evaluation

Lennart M. Reimann, Evgenii Rezunov, Dominik Germek +4

Logic locking secures hardware designs in untrusted foundries by incorporating key-driven gates to obscure the original blueprint. While this method safeguards the integrated circu…