14 citations · 66 across the 23 of their papers we have counts for
5 papers · 1 filter
ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction
Luca Collini, Jitendra Bhandari, Chiara Muscari Tomajoli +6
In the modern global Integrated Circuit (IC) supply chain, protecting intellectual property (IP) is a complex challenge, and balancing IP loss risk and added cost for theft counter…
MARVEL: Multi-Agent RTL Vulnerability Extraction using Large Language Models
Luca Collini, Baleegh Ahmad, Joey Ah-kiow +1
Hardware security verification is a challenging and time-consuming task. Design engineers may use formal verification, linting, and functional simulation tests, coupled with analys…
LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs
Baleegh Ahmad, Hammond Pearce, Ramesh Karri +1
While static analysis is useful in detecting early-stage hardware security bugs, its efficacy is limited because it requires information to form checks and is often unable to expla…
The Impact of Logic Locking on Confidentiality: An Automated Evaluation
Lennart M. Reimann, Evgenii Rezunov, Dominik Germek +4
Logic locking secures hardware designs in untrusted foundries by incorporating key-driven gates to obscure the original blueprint. While this method safeguards the integrated circu…
An Empirical Evaluation of LLMs for Solving Offensive Security Challenges
Minghao Shao, Boyuan Chen, Sofija Jancheska +4
Capture The Flag (CTF) challenges are puzzles related to computer security scenarios. With the advent of large language models (LLMs), more and more CTF participants are using LLMs…