300 citations · 906 across the 12 of their papers we have counts for
10 papers · 1 filter
Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package
Eduard Alarcón, Sergi Abadal, Fabio Sebastiano +9
The grand challenge of scaling up quantum computers requires a full-stack architectural standpoint. In this position paper, we will present the vision of a new generation of scalab…
Real-Time Decoding for Fault-Tolerant Quantum Computing: Progress, Challenges and Outlook
Francesco Battistel, Christopher Chamberland, Kauser Johar +5
Quantum computing is poised to solve practically useful problems which are computationally intractable for classical supercomputers. However, the current generation of quantum comp…
SpinQ: Compilation strategies for scalable spin-qubit architectures
Nikiforos Paraskevopoulos, Fabio Sebastiano, Carmen G. Almudever +1
Despite NISQ devices being severely constrained, hardware- and algorithm-aware quantum circuit mapping techniques have been developed to enable successful algorithm executions. Not…
Neural-Network Decoders for Quantum Error Correction using Surface Codes:A Space Exploration of the Hardware Cost-Performance Trade-Offs
Ramon Overwater, Masoud Babaie, Fabio Sebastiano
Quantum Error Correction (QEC) is required in quantum computers to mitigate the effect of errors on physical qubits. When adopting a QEC scheme based on surface codes, error decodi…
Spiderweb array: A sparse spin-qubit array
Jelmer M. Boter, Juan P. Dehollain, Jeroen P. G. van Dijk +8
One of the main bottlenecks in the pursuit of a large-scale--chip-based quantum computer is the large number of control signals needed to operate qubit systems. As system sizes sca…
CMOS-based cryogenic control of silicon quantum circuits
Xiao Xue, Bishnu Patra, Jeroen P. G. van Dijk +21
The most promising quantum algorithms require quantum processors hosting millions of quantum bits when targeting practical applications. A major challenge towards large-scale quant…
A sparse spin qubit array with integrated control electronics
Jelmer M. Boter, Juan P. Dehollain, Jeroen P. G. van Dijk +6
Current implementations of quantum computers suffer from large numbers of control lines per qubit, becoming unmanageable with system scale up. Here, we discuss a sparse spin-qubit…
The electronic interface for quantum processors
Jeroen P. G. van Dijk, Edoardo Charbon, Fabio Sebastiano
Quantum computers can potentially provide an unprecedented speed-up with respect to traditional computers. However, a significant increase in the number of quantum bits (qubits) an…
The impact of classical control electronics on qubit fidelity
Jeroen P. G. van Dijk, Erika Kawakami, Raymond N. Schouten +5
Quantum processors rely on classical electronic controllers to manipulate and read out the quantum state. As the performance of the quantum processor improves, non-idealities in th…
Quantum information density scaling and qubit operation time constraints of CMOS silicon based quantum computer architectures
Davide Rotta, Fabio Sebastiano, Edoardo Charbon +1
Even the quantum simulation of simple molecules such as FeS requires more than 10 qubits. In order to assess such a multimillion scale of identical qubits and control l…