85 citations · 331 across the 24 of their papers we have counts for
30 papers
Mapping of CNNs on multi-core RRAM-based CIM architectures
Rebecca Pelke, Nils Bosbach, Jose Cubero +3
RRAM-based multi-core systems improve the energy efficiency and performance of CNNs. Thereby, the distributed parallel execution of convolutional layers causes critical data depend…
SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors
Lennart M. Reimann, Jonathan Wiesner, Dominik Sisejkovic +2
Despite its ever-increasing impact, security is not considered as a design objective in commercial electronic design automation (EDA) tools. This results in vulnerabilities being o…
parti-gem5: gem5's Timing Mode Parallelised
José Cubero-Cascante, Niko Zurstraßen, Jörn Nöller +2
Detailed timing models are indispensable tools for the design space exploration of Multiprocessor Systems on Chip (MPSoCs). As core counts continue to increase, the complexity in m…
Gate Camouflaging Using Reconfigurable ISFET-Based Threshold Voltage Defined Logic
Elmira Moussavi, Animesh Singh, Dominik Sisejkovic +6
Most chip designers outsource the manufacturing of their integrated circuits (ICs) to external foundries due to the exorbitant cost and complexity of the process. This involvement…
Automated Information Flow Analysis for Integrated Computing-in-Memory Modules
Lennart M. Reimann, Felix Staudigl, Rainer Leupers
Novel non-volatile memory (NVM) technologies offer high-speed and high-density data storage. In addition, they overcome the von Neumann bottleneck by enabling computing-in-memory (…
Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware
Felix Staudigl, Thorben Fetz, Rebecca Pelke +4
Logic-in-memory (LIM) describes the execution of logic gates within memristive crossbar structures, promising to improve performance and energy efficiency. Utilizing only binary va…
Quantitative Information Flow for Hardware: Advancing the Attack Landscape
Lennart M. Reimann, Sarp Erdönmez, Dominik Sisejkovic +1
Security still remains an afterthought in modern Electronic Design Automation (EDA) tools, which solely focus on enhancing performance and reducing the chip size. Typically, the se…
A Temperature Independent Readout Circuit for ISFET-Based Sensor Applications
Elmira Moussavi, Dominik Sisejkovic, Animesh Singh +5
The ion-sensitive field-effect transistor (ISFET) is an emerging technology that has received much attention in numerous research areas, including biochemistry, medicine, and secur…
PA-PUF: A Novel Priority Arbiter PUF
Simranjeet Singh, Srinivasu Bodapati, Sachin Patkar +3
This paper proposes a 3-input arbiter-based novel physically unclonable function (PUF) design. Firstly, a 3-input priority arbiter is designed using a simple arbiter, two multiplex…
NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool
Nils Bosbach, Lukas Jünger, Jan Moritz Joseph +1
The increasing complexity of systems-on-a-chip requires the continuous development of electronic design automation tools. Nowadays, the simulation of systems-on-a-chip using virtua…
EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs
Yee Yang Tan, Felix Staudigl, Lukas Jünger +3
Networks-on-Chips (NoCs) recently became widely used, from multi-core CPUs to edge-AI accelerators. Emulation on FPGAs promises to accelerate their RTL modeling compared to slow si…
Designing ML-Resilient Locking at Register-Transfer Level
Dominik Sisejkovic, Luca Collini, Benjamin Tan +3
Various logic-locking schemes have been proposed to protect hardware from intellectual property piracy and malicious design modifications. Since traditional locking techniques are…
X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation
Felix Staudigl, Karl J. X. Sturm, Maximilian Bartel +5
Memristor-based crossbar arrays represent a promising emerging memory technology to replace conventional memories by offering a high density and enabling computing-in-memory (CIM)…
pHGen: A pH-Based Key Generation Mechanism Using ISFETs
Elmira Moussavi, Dominik Sisejkovic, Fabian Brings +7
Digital keys are a fundamental component of many hardware- and software-based security mechanisms. However, digital keys are limited to binary values and easily exploitable when st…
A Parallel SystemC Virtual Platform for Neuromorphic Architectures
Melvin Galicia, Farhad Merchant, Rainer Leupers
With the increasing interest in neuromorphic computing, designers of embedded systems face the challenge of efficiently simulating such platforms to enable architecture design expl…
NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories
Felix Staudigl, Hazem Al Indari, Daniel Schön +6
Emerging non-volatile memory (NVM) technologies offer unique advantages in energy efficiency, latency, and features such as computing-in-memory. Consequently, emerging NVM technolo…
QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog
Lennart M. Reimann, Luca Hanel, Dominik Sisejkovic +2
The enormous amount of code required to design modern hardware implementations often leads to critical vulnerabilities being overlooked. Especially vulnerabilities that compromise…
Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks
Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann +1
Logic locking has emerged as a prominent key-driven technique to protect the integrity of integrated circuits. However, novel machine-learning-based attacks have recently been intr…
Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities
Dominik Sisejkovic, Lennart M. Reimann, Elmira Moussavi +2
In the past decade, a lot of progress has been made in the design and evaluation of logic locking; a premier technique to safeguard the integrity of integrated circuits throughout…
Brightening the Optical Flow through Posit Arithmetic
Vinay Saxena, Ankitha Reddy, Jonathan Neudorfer +4
As new technologies are invented, their commercial viability needs to be carefully examined along with their technical merits and demerits. The posit data format, proposed as a dro…
ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework
Farhad Merchant, Dominik Sisejkovic, Lennart M. Reimann +3
With the growing demands of consumer electronic products, the computational requirements are increasing exponentially. Due to the applications' computational needs, the computer ar…
An Investigation on Inherent Robustness of Posit Data Representation
Ihsen Alouani, Anouar Ben Khalifa, Farhad Merchant +1
As the dimensions and operating voltages of computer electronics shrink to cope with consumers' demand for higher performance and lower power consumption, circuit sensitivity to so…
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators
Jan Moritz Joseph, Ananda Samajdar, Lingjun Zhu +4
The everlasting demand for higher computing power for deep neural networks (DNNs) drives the development of parallel computing architectures. 3D integration, in which chips are int…
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach
Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann +3
Logic locking is a prominent technique to protect the integrity of hardware designs throughout the integrated circuit design and fabrication flow. However, in recent years, the sec…