85 citations · 331 across the 24 of their papers we have counts for
6 papers · 1 filter
Mapping of CNNs on multi-core RRAM-based CIM architectures
Rebecca Pelke, Nils Bosbach, Jose Cubero +3
RRAM-based multi-core systems improve the energy efficiency and performance of CNNs. Thereby, the distributed parallel execution of convolutional layers causes critical data depend…
SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors
Lennart M. Reimann, Jonathan Wiesner, Dominik Sisejkovic +2
Despite its ever-increasing impact, security is not considered as a design objective in commercial electronic design automation (EDA) tools. This results in vulnerabilities being o…
parti-gem5: gem5's Timing Mode Parallelised
José Cubero-Cascante, Niko Zurstraßen, Jörn Nöller +2
Detailed timing models are indispensable tools for the design space exploration of Multiprocessor Systems on Chip (MPSoCs). As core counts continue to increase, the complexity in m…
Gate Camouflaging Using Reconfigurable ISFET-Based Threshold Voltage Defined Logic
Elmira Moussavi, Animesh Singh, Dominik Sisejkovic +6
Most chip designers outsource the manufacturing of their integrated circuits (ICs) to external foundries due to the exorbitant cost and complexity of the process. This involvement…
Automated Information Flow Analysis for Integrated Computing-in-Memory Modules
Lennart M. Reimann, Felix Staudigl, Rainer Leupers
Novel non-volatile memory (NVM) technologies offer high-speed and high-density data storage. In addition, they overcome the von Neumann bottleneck by enabling computing-in-memory (…
Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware
Felix Staudigl, Thorben Fetz, Rebecca Pelke +4
Logic-in-memory (LIM) describes the execution of logic gates within memristive crossbar structures, promising to improve performance and energy efficiency. Utilizing only binary va…