85 citations · 331 across the 24 of their papers we have counts for
12 papers · 1 filter
Mapping of CNNs on multi-core RRAM-based CIM architectures
Rebecca Pelke, Nils Bosbach, Jose Cubero +3
RRAM-based multi-core systems improve the energy efficiency and performance of CNNs. Thereby, the distributed parallel execution of convolutional layers causes critical data depend…
parti-gem5: gem5's Timing Mode Parallelised
José Cubero-Cascante, Niko Zurstraßen, Jörn Nöller +2
Detailed timing models are indispensable tools for the design space exploration of Multiprocessor Systems on Chip (MPSoCs). As core counts continue to increase, the complexity in m…
NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool
Nils Bosbach, Lukas Jünger, Jan Moritz Joseph +1
The increasing complexity of systems-on-a-chip requires the continuous development of electronic design automation tools. Nowadays, the simulation of systems-on-a-chip using virtua…
EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs
Yee Yang Tan, Felix Staudigl, Lukas Jünger +3
Networks-on-Chips (NoCs) recently became widely used, from multi-core CPUs to edge-AI accelerators. Emulation on FPGAs promises to accelerate their RTL modeling compared to slow si…
A Parallel SystemC Virtual Platform for Neuromorphic Architectures
Melvin Galicia, Farhad Merchant, Rainer Leupers
With the increasing interest in neuromorphic computing, designers of embedded systems face the challenge of efficiently simulating such platforms to enable architecture design expl…
Brightening the Optical Flow through Posit Arithmetic
Vinay Saxena, Ankitha Reddy, Jonathan Neudorfer +4
As new technologies are invented, their commercial viability needs to be carefully examined along with their technical merits and demerits. The posit data format, proposed as a dro…
ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework
Farhad Merchant, Dominik Sisejkovic, Lennart M. Reimann +3
With the growing demands of consumer electronic products, the computational requirements are increasing exponentially. Due to the applications' computational needs, the computer ar…
An Investigation on Inherent Robustness of Posit Data Representation
Ihsen Alouani, Anouar Ben Khalifa, Farhad Merchant +1
As the dimensions and operating voltages of computer electronics shrink to cope with consumers' demand for higher performance and lower power consumption, circuit sensitivity to so…
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators
Jan Moritz Joseph, Ananda Samajdar, Lingjun Zhu +4
The everlasting demand for higher computing power for deep neural networks (DNNs) drives the development of parallel computing architectures. 3D integration, in which chips are int…
CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism
Niraj Sharma, Riya Jain, Madhumita Mohan +4
Many engineering and scientific applications require high precision arithmetic. IEEE~754-2008 compliant (floating-point) arithmetic is the de facto standard for performing these co…
An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration
Andreas Bytyn, Rainer Leupers, Gerd Ascheid
In recent years, neural networks have surpassed classical algorithms in areas such as object recognition, e.g. in the well-known ImageNet challenge. As a result, great effort is be…
A Scalable VLSI Architecture for Soft-Input Soft-Output Depth-First Sphere Decoding
Ernst Martin Witte, Filippo Borlenghi, Gerd Ascheid +2
Multiple-input multiple-output (MIMO) wireless transmission imposes huge challenges on the design of efficient hardware architectures for iterative receivers. A major challenge is…