Method for efficient large-scale cryogenic characterization of CMOS technologies

Abstract

Semiconductor integrated circuits operated at cryogenic temperature will play an essential role in quantum computing architectures. These can offer equivalent or superior performance to their room-temperature counterparts while enabling a scaling up of the total number of qubits under control. Silicon integrated circuits can be operated at a temperature stage of a cryogenic system where cooling power is sufficient ($\sim$3.5+ K) to allow for analog signal chain components (e.g. amplifiers and mixers), local signal synthesis, signal digitization, and control logic. A critical stage in cryo-electronics development is the characterization of individual transistor devices in a particular technology node at cryogenic temperatures. This data enables the creation of a process design kit (PDK) to model devices and simulate integrated circuits operating well below the minimum standard temperature ranges covered by foundry-released models (e.g. -55 °C). Here, an efficient approach to the characterization of large numbers of components at cryogenic temperature is reported. We developed a system to perform DC measurements with Kelvin sense of individual transistors at 4.2 K using integrated on-die multiplexers, enabling bulk characterization of thousands of devices with no physical change to the measurement setup.

10 pages, 5 figures, 2 tables

References in corpus (10)

• CMOS-based cryogenic control of silicon quantum circuits
• Scaling silicon-based quantum computing using CMOS technology: State-of-the-art, Challenges and Perspectives
• A hole spin qubit in a fin field-effect transistor above 4 kelvin
• Probing single electrons across 300 mm spin qubit wafers
• Probing quantum devices with radio-frequency reflectometry
• Ion traps fabricated in a CMOS foundry
• Overcoming I/O bottleneck in superconducting quantum computing: multiplexed qubit control with ultra-low-power, base-temperature cryo-CMOS multiplexer
• Characterization and Modeling of Native MOSFETs Down to 4.2 K
• CMOS on-chip thermometry at deep cryogenic temperatures
• Superconducting routing platform for large-scale integration of quantum technologies

Cited by in corpus (2)

• An Integrated Deep-Cryogenic Temperature Sensor in CMOS Technology for Quantum Computing Applications
• Reproducibility and variability in commercial SiC MOSFETs at deep-cryogenic temperatures