ASSURE: RTL Locking Against an Untrusted Foundry

Abstract

Semiconductor design companies are integrating proprietary intellectual property (IP) blocks to build custom integrated circuits (IC) and fabricate them in a third-party foundry. Unauthorized IC copies cost these companies billions of dollars annually. While several methods have been proposed for hardware IP obfuscation, they operate on the gate-level netlist, i.e., after the synthesis tools embed the semantic information into the netlist. We propose ASSURE to protect hardware IP modules operating on the register-transfer level (RTL) description. The RTL approach has three advantages: (i) it allows designers to obfuscate IP cores generated with many different methods (e.g., hardware generators, high-level synthesis tools, and pre-existing IPs). (ii) it obfuscates the semantics of an IC before logic synthesis; (iii) it does not require modifications to EDA flows. We perform a cost and security assessment of ASSURE.

arXiv commentAccepted for publication in IEEE Transactions on VLSI Systems on 06-Apr-2021

References in corpus (4)

• Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach
• Logic Locking for Secure Outsourced Chip Fabrication: A New Attack and Provably Secure Defense Mechanism
• Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking
• On Secure and Usable Program Obfuscation: A Survey

Cited by in corpus (5)

• Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks
• Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities
• ALICE: An Automatic Design Flow for eFPGA Redaction
• Optimizing the Use of Behavioral Locking for High-Level Synthesis
• ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction