203 citations · 998 across the 44 of their papers we have counts for
45 papers
VeriGen: A Large Language Model for Verilog Code Generation
Shailja Thakur, Baleegh Ahmad, Hammond Pearce +4
In this study, we explore the capability of Large Language Models (LLMs) to automate hardware design by generating high-quality Verilog code, a common language for designing and mo…
Causative Cyberattacks on Online Learning-based Automated Demand Response Systems
Samrat Acharya, Yury Dvorkin, Ramesh Karri
Power utilities are adopting Automated Demand Response (ADR) to replace the costly fuel-fired generators and to preempt congestion during peak electricity demand. Similarly, third-…
FLAG: Finding Line Anomalies (in code) with Generative AI
Baleegh Ahmad, Benjamin Tan, Ramesh Karri +1
Code contains security and functional bugs. The process of identifying and localizing them is difficult and relies on human labor. In this work, we present a novel approach (FLAG)…
INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search
Animesh Basak Chowdhury, Marco Romanelli, Benjamin Tan +2
Logic synthesis is the first and most vital step in chip design. This steps converts a chip specification written in a hardware description language (such as Verilog) into an optim…
(Security) Assertions by Large Language Models
Rahul Kande, Hammond Pearce, Benjamin Tan +4
The security of computer systems typically relies on a hardware root of trust. As vulnerabilities in hardware can have severe implications on a system, there is a need for techniqu…
Chip-Chat: Challenges and Opportunities in Conversational Hardware Design
Jason Blocklove, Siddharth Garg, Ramesh Karri +1
Modern hardware design starts with specifications provided in natural language. These are then translated by hardware engineers into appropriate Hardware Description Languages (HDL…
REMaQE: Reverse Engineering Math Equations from Executables
Meet Udeshi, Prashanth Krishnamurthy, Hammond Pearce +2
Cybersecurity attacks on embedded devices for industrial control systems and cyber-physical systems may cause catastrophic physical damage as well as economic loss. This could be a…
ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning
Animesh Basak Chowdhury, Lilas Alrahis, Luca Collini +5
Oracle-less machine learning (ML) attacks have broken various logic locking schemes. Regular synthesis, which is tailored for area-power-delay optimization, yields netlists where k…
Fixing Hardware Security Bugs with Large Language Models
Baleegh Ahmad, Shailja Thakur, Benjamin Tan +2
Novel AI-based code-writing Large Language Models (LLMs) such as OpenAI's Codex have demonstrated capabilities in many coding-adjacent domains. In this work we consider how LLMs ma…
A survey of Digital Manufacturing Hardware and Software Trojans
Prithwish Basu Roy, Mudit Bhargava, Chia-Yun Chang +4
Digital Manufacturing (DM) refers to the on-going adoption of smarter, more agile manufacturing processes and cyber-physical systems. This includes modern techniques and technologi…
Benchmarking Large Language Models for Automated Verilog RTL Code Generation
Shailja Thakur, Baleegh Ahmad, Zhenxing Fan +5
Automating hardware design could obviate a significant amount of human error from the engineering process and lead to fewer errors. Verilog is a popular hardware description langua…
Don't CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design
Baleegh Ahmad, Wei-Kai Liu, Luca Collini +9
To help prevent hardware security vulnerabilities from propagating to later design stages where fixes are costly, it is crucial to identify security concerns as early as possible,…
Lost at C: A User Study on the Security Implications of Large Language Model Code Assistants
Gustavo Sandoval, Hammond Pearce, Teo Nys +3
Large Language Models (LLMs) such as OpenAI Codex are increasingly being used as AI-based coding assistants. Understanding the impact of these tools on developers' code is paramoun…
High-Level Approaches to Hardware Security: A Tutorial
Hammond Pearce, Ramesh Karri, Benjamin Tan
Designers use third-party intellectual property (IP) cores and outsource various steps in the integrated circuit (IC) design and manufacturing flow. As a result, security vulnerabi…
ALICE: An Automatic Design Flow for eFPGA Redaction
Chiara Muscari Tomajoli, Luca Collini, Jitendra Bhandari +6
Fabricating an integrated circuit is becoming unaffordable for many semiconductor design houses. Outsourcing the fabrication to a third-party foundry requires methods to protect th…
Designing ML-Resilient Locking at Register-Transfer Level
Dominik Sisejkovic, Luca Collini, Benjamin Tan +3
Various logic-locking schemes have been proposed to protect hardware from intellectual property piracy and malicious design modifications. Since traditional locking techniques are…
CoFHEE: A Co-processor for Fully Homomorphic Encryption Execution (Extended Version)
Mohammed Nabeel, Homer Gamil, Deepraj Soni +6
The migration of computation to the cloud has raised concerns regarding the security and privacy of sensitive data, as their need to be decrypted before processing, renders them su…
Fuzzing+Hardware Performance Counters-Based Detection of Algorithm Subversion Attacks on Post-Quantum Signature Schemes
Animesh Basak Chowdhury, Anushree Mahapatra, Deepraj Soni +1
NIST is standardizing Post Quantum Cryptography (PQC) algorithms that are resilient to the computational capability of quantum computers. Past works show malicious subversion with…
Pop Quiz! Can a Large Language Model Help With Reverse Engineering?
Hammond Pearce, Benjamin Tan, Prashanth Krishnamurthy +3
Large language models (such as OpenAI's Codex) have demonstrated impressive zero-shot multi-task capabilities in the software domain, including code explanation. In this work, we e…
HOLL: Program Synthesis for Higher OrderLogic Locking
Gourav Takhar, Ramesh Karri, Christian Pilato +1
Logic locking "hides" the functionality of a digital circuit to protect it from counterfeiting, piracy, and malicious design modifications. The original design is transformed into…
Examining Zero-Shot Vulnerability Repair with Large Language Models
Hammond Pearce, Benjamin Tan, Baleegh Ahmad +2
Human developers can produce code with cybersecurity bugs. Can emerging 'smart' code completion tools help repair those bugs? In this work, we examine the use of large language mod…
Not All Fabrics Are Created Equal: Exploring eFPGA Parameters For IP Redaction
Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan +6
Semiconductor design houses rely on third-party foundries to manufacture their integrated circuits (IC). While this trend allows them to tackle fabrication costs, it introduces sec…
Exploring eFPGA-based Redaction for IP Protection
Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan +6
Recently, eFPGA-based redaction has been proposed as a promising solution for hiding parts of a digital design from untrusted entities, where legitimate end-users can restore funct…
OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesis
Animesh Basak Chowdhury, Benjamin Tan, Ramesh Karri +1
Logic synthesis is a challenging and widely-researched combinatorial optimization problem during integrated circuit (IC) design. It transforms a high-level description of hardware…