DAVE: Deriving Automatically Verilog from English

Abstract

While specifications for digital systems are provided in natural language, engineers undertake significant efforts to translate them into the programming languages understood by compilers for digital systems. Automating this process allows designers to work with the language in which they are most comfortable --the original natural language -- and focus instead on other downstream design challenges. We explore the use of state-of-the-art machine learning (ML) to automatically derive Verilog snippets from English via fine-tuning GPT-2, a natural language ML system. We describe our approach for producing a suitable dataset of novice-level digital design tasks and provide a detailed exploration of GPT-2, finding encouraging translation performance across our task sets (94.8% correct), with the ability to handle both simple and abstract design tasks.

arXiv comment6 pages, 2 figures

References in corpus (1)

• Recurrent Neural Network for Text Classification with Multi-Task Learning

Cited by in corpus (8)

• Chip-Chat: Challenges and Opportunities in Conversational Hardware Design
• (Security) Assertions by Large Language Models
• Fixing Hardware Security Bugs with Large Language Models
• Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework
• LLM-aided explanations of EDA synthesis errors
• Evaluating LLMs for Hardware Design and Test
• Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization
• OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design