77 citations · 464 across the 32 of their papers we have counts for
33 papers
Toward Automated Potential Primary Asset Identification in Verilog Designs
Subroto Kumer Deb Nath, Benjamin Tan
With greater design complexity, the challenge to anticipate and mitigate security issues provides more responsibility for the designer. As hardware provides the foundation of a sec…
Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback
Jason Blocklove, Shailja Thakur, Benjamin Tan +3
Traditionally, digital hardware designs are written in the Verilog hardware description language (HDL) and debugged manually by engineers. This can be time-consuming and error-pron…
The Quest to Build Trust Earlier in Digital Design
Benjamin Tan
The ever-rising complexity of computer systems presents challenges for maintaining security and trust throughout their lifetime. As hardware forms the foundation of a secure system…
An Investigation of Hardware Security Bug Characteristics in Open-Source Projects
Joey Ah-kiow, Benjamin Tan
Hardware security is an important concern of system security as vulnerabilities can arise from design errors introduced throughout the development lifecycle. Recent works have prop…
Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization
Animesh Basak Chowdhury, Marco Romanelli, Benjamin Tan +2
Logic synthesis, a pivotal stage in chip design, entails optimizing chip specifications encoded in hardware description languages like Verilog into highly efficient implementations…
Theoretical Patchability Quantification for IP-Level Hardware Patching Designs
Wei-Kai Liu, Benjamin Tan, Jason M. Fung +1
As the complexity of System-on-Chip (SoC) designs continues to increase, ensuring thorough verification becomes a significant challenge for system integrators. The complexity of ve…
AutoChip: Automating HDL Generation Using LLM Feedback
Shailja Thakur, Jason Blocklove, Hammond Pearce +3
Traditionally, designs are written in Verilog hardware description language (HDL) and debugged by hardware engineers. While this approach is effective, it is time-consuming and err…
Are Emily and Greg Still More Employable than Lakisha and Jamal? Investigating Algorithmic Hiring Bias in the Era of ChatGPT
Akshaj Kumar Veldanda, Fabian Grob, Shailja Thakur +4
Large Language Models (LLMs) such as GPT-3.5, Bard, and Claude exhibit applicability across numerous tasks. One domain of interest is their use in algorithmic hiring, specifically…
VeriGen: A Large Language Model for Verilog Code Generation
Shailja Thakur, Baleegh Ahmad, Hammond Pearce +4
In this study, we explore the capability of Large Language Models (LLMs) to automate hardware design by generating high-quality Verilog code, a common language for designing and mo…
FLAG: Finding Line Anomalies (in code) with Generative AI
Baleegh Ahmad, Benjamin Tan, Ramesh Karri +1
Code contains security and functional bugs. The process of identifying and localizing them is difficult and relies on human labor. In this work, we present a novel approach (FLAG)…
INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search
Animesh Basak Chowdhury, Marco Romanelli, Benjamin Tan +2
Logic synthesis is the first and most vital step in chip design. This steps converts a chip specification written in a hardware description language (such as Verilog) into an optim…
(Security) Assertions by Large Language Models
Rahul Kande, Hammond Pearce, Benjamin Tan +4
The security of computer systems typically relies on a hardware root of trust. As vulnerabilities in hardware can have severe implications on a system, there is a need for techniqu…
ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning
Animesh Basak Chowdhury, Lilas Alrahis, Luca Collini +5
Oracle-less machine learning (ML) attacks have broken various logic locking schemes. Regular synthesis, which is tailored for area-power-delay optimization, yields netlists where k…
Fixing Hardware Security Bugs with Large Language Models
Baleegh Ahmad, Shailja Thakur, Benjamin Tan +2
Novel AI-based code-writing Large Language Models (LLMs) such as OpenAI's Codex have demonstrated capabilities in many coding-adjacent domains. In this work we consider how LLMs ma…
Benchmarking Large Language Models for Automated Verilog RTL Code Generation
Shailja Thakur, Baleegh Ahmad, Zhenxing Fan +5
Automating hardware design could obviate a significant amount of human error from the engineering process and lead to fewer errors. Verilog is a popular hardware description langua…
Don't CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design
Baleegh Ahmad, Wei-Kai Liu, Luca Collini +9
To help prevent hardware security vulnerabilities from propagating to later design stages where fixes are costly, it is crucial to identify security concerns as early as possible,…
High-Level Approaches to Hardware Security: A Tutorial
Hammond Pearce, Ramesh Karri, Benjamin Tan
Designers use third-party intellectual property (IP) cores and outsource various steps in the integrated circuit (IC) design and manufacturing flow. As a result, security vulnerabi…
ALICE: An Automatic Design Flow for eFPGA Redaction
Chiara Muscari Tomajoli, Luca Collini, Jitendra Bhandari +6
Fabricating an integrated circuit is becoming unaffordable for many semiconductor design houses. Outsourcing the fabrication to a third-party foundry requires methods to protect th…
MALICE: Manipulation Attacks on Learned Image ComprEssion
Kang Liu, Di Wu, Yiru Wang +3
Deep learning techniques have shown promising results in image compression, with competitive bitrate and image reconstruction quality from compressed latent. However, while image c…
Designing ML-Resilient Locking at Register-Transfer Level
Dominik Sisejkovic, Luca Collini, Benjamin Tan +3
Various logic-locking schemes have been proposed to protect hardware from intellectual property piracy and malicious design modifications. Since traditional locking techniques are…
Too Big to Fail? Active Few-Shot Learning Guided Logic Synthesis
Animesh Basak Chowdhury, Benjamin Tan, Ryan Carey +3
Generating sub-optimal synthesis transformation sequences ("synthesis recipe") is an important problem in logic synthesis. Manually crafted synthesis recipes have poor quality. Sta…
Pop Quiz! Can a Large Language Model Help With Reverse Engineering?
Hammond Pearce, Benjamin Tan, Prashanth Krishnamurthy +3
Large language models (such as OpenAI's Codex) have demonstrated impressive zero-shot multi-task capabilities in the software domain, including code explanation. In this work, we e…
Examining Zero-Shot Vulnerability Repair with Large Language Models
Hammond Pearce, Benjamin Tan, Baleegh Ahmad +2
Human developers can produce code with cybersecurity bugs. Can emerging 'smart' code completion tools help repair those bugs? In this work, we examine the use of large language mod…
Not All Fabrics Are Created Equal: Exploring eFPGA Parameters For IP Redaction
Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan +6
Semiconductor design houses rely on third-party foundries to manufacture their integrated circuits (IC). While this trend allows them to tackle fabrication costs, it introduces sec…