29 citations · 102 across the 19 of their papers we have counts for
8 papers · 1 filter
Theoretical Patchability Quantification for IP-Level Hardware Patching Designs
Wei-Kai Liu, Benjamin Tan, Jason M. Fung +1
As the complexity of System-on-Chip (SoC) designs continues to increase, ensuring thorough verification becomes a significant challenge for system integrators. The complexity of ve…
AutoChip: Automating HDL Generation Using LLM Feedback
Shailja Thakur, Jason Blocklove, Hammond Pearce +3
Traditionally, designs are written in Verilog hardware description language (HDL) and debugged by hardware engineers. While this approach is effective, it is time-consuming and err…
Are Emily and Greg Still More Employable than Lakisha and Jamal? Investigating Algorithmic Hiring Bias in the Era of ChatGPT
Akshaj Kumar Veldanda, Fabian Grob, Shailja Thakur +4
Large Language Models (LLMs) such as GPT-3.5, Bard, and Claude exhibit applicability across numerous tasks. One domain of interest is their use in algorithmic hiring, specifically…
VeriGen: A Large Language Model for Verilog Code Generation
Shailja Thakur, Baleegh Ahmad, Hammond Pearce +4
In this study, we explore the capability of Large Language Models (LLMs) to automate hardware design by generating high-quality Verilog code, a common language for designing and mo…
FLAG: Finding Line Anomalies (in code) with Generative AI
Baleegh Ahmad, Benjamin Tan, Ramesh Karri +1
Code contains security and functional bugs. The process of identifying and localizing them is difficult and relies on human labor. In this work, we present a novel approach (FLAG)…
INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search
Animesh Basak Chowdhury, Marco Romanelli, Benjamin Tan +2
Logic synthesis is the first and most vital step in chip design. This steps converts a chip specification written in a hardware description language (such as Verilog) into an optim…