203 citations · 677 across the 32 of their papers we have counts for
32 papers
PCB-QA: Evaluating LLMs over the First Printed Circuit Board Design Question-Answer Dataset
Sahana Srinivasan, Benjamin Tan, Benjamin Turnbull +1
Large Language Models (LLMs) have demonstrated capabilities in electronic design automation (EDA) for integrated circuits. However, their applications in printed circuit board (PCB…
Surveying GenAI-based Automation in Printed Circuit Board Design and Test
Sahana Srinivasan, Benjamin Turnbull, Hammond Pearce
Generative artificial intelligence (GenAI) is increasingly used for applications in the hardware and software domains. It purports to reduce the manual effort involved in the devel…
Towards LLM-based Root Cause Analysis of Hardware Design Failures
Siyu Qiu, Muzhi Wang, Raheel Afsharmazayejani +3
With advances in large language models (LLMs), new opportunities have emerged to develop tools that support the digital hardware design process. In this work, we explore how LLMs c…
LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs
Baleegh Ahmad, Hammond Pearce, Ramesh Karri +1
While static analysis is useful in detecting early-stage hardware security bugs, its efficacy is limited because it requires information to form checks and is often unable to expla…
Large Language Models and Attention-Based AI for Hardware Design and Security: Progress, Challenges, and Opportunities
Sujan Ghimire, Parsa Mirfasihi, Muhtasim Alam Chowdhury +9
Recent advances in attention-based artificial intelligence (AI) models have unlocked vast potential to automate digital hardware design while enhancing and strengthening security m…
Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback
Jason Blocklove, Shailja Thakur, Benjamin Tan +3
Traditionally, digital hardware designs are written in the Verilog hardware description language (HDL) and debugged manually by engineers. This can be time-consuming and error-pron…
Evaluating LLMs for Hardware Design and Test
Jason Blocklove, Siddharth Garg, Ramesh Karri +1
Large Language Models (LLMs) have demonstrated capabilities for producing code in Hardware Description Languages (HDLs). However, most of the focus remains on their abilities to wr…
OffRAMPS: An FPGA-based Intermediary for Analysis and Modification of Additive Manufacturing Control Systems
Jason Blocklove, Md Raz, Prithwish Basu Roy +4
Cybersecurity threats in Additive Manufacturing (AM) are an increasing concern as AM adoption continues to grow. AM is now being used for parts in the aerospace, transportation, an…
LLM-aided explanations of EDA synthesis errors
Siyu Qiu, Benjamin Tan, Hammond Pearce
Training new engineers in digital design is a challenge, particularly when it comes to teaching the complex electronic design automation (EDA) tooling used in this domain. Learners…
AutoChip: Automating HDL Generation Using LLM Feedback
Shailja Thakur, Jason Blocklove, Hammond Pearce +3
Traditionally, designs are written in Verilog hardware description language (HDL) and debugged by hardware engineers. While this approach is effective, it is time-consuming and err…
Towards the Imagenets of ML4EDA
Animesh Basak Chowdhury, Shailja Thakur, Hammond Pearce +2
Despite the growing interest in ML-guided EDA tools from RTL to GDSII, there are no standard datasets or prototypical learning tasks defined for the EDA problem domain. Experience…
Are Emily and Greg Still More Employable than Lakisha and Jamal? Investigating Algorithmic Hiring Bias in the Era of ChatGPT
Akshaj Kumar Veldanda, Fabian Grob, Shailja Thakur +4
Large Language Models (LLMs) such as GPT-3.5, Bard, and Claude exhibit applicability across numerous tasks. One domain of interest is their use in algorithmic hiring, specifically…
Dcc --help: Generating Context-Aware Compiler Error Explanations with Large Language Models
Andrew Taylor, Alexandra Vassar, Jake Renzella +1
In the challenging field of introductory programming, high enrollments and failure rates drive us to explore tools and systems to enhance student outcomes, especially automated too…
VeriGen: A Large Language Model for Verilog Code Generation
Shailja Thakur, Baleegh Ahmad, Hammond Pearce +4
In this study, we explore the capability of Large Language Models (LLMs) to automate hardware design by generating high-quality Verilog code, a common language for designing and mo…
FLAG: Finding Line Anomalies (in code) with Generative AI
Baleegh Ahmad, Benjamin Tan, Ramesh Karri +1
Code contains security and functional bugs. The process of identifying and localizing them is difficult and relies on human labor. In this work, we present a novel approach (FLAG)…
(Security) Assertions by Large Language Models
Rahul Kande, Hammond Pearce, Benjamin Tan +4
The security of computer systems typically relies on a hardware root of trust. As vulnerabilities in hardware can have severe implications on a system, there is a need for techniqu…
Chip-Chat: Challenges and Opportunities in Conversational Hardware Design
Jason Blocklove, Siddharth Garg, Ramesh Karri +1
Modern hardware design starts with specifications provided in natural language. These are then translated by hardware engineers into appropriate Hardware Description Languages (HDL…
REMaQE: Reverse Engineering Math Equations from Executables
Meet Udeshi, Prashanth Krishnamurthy, Hammond Pearce +2
Cybersecurity attacks on embedded devices for industrial control systems and cyber-physical systems may cause catastrophic physical damage as well as economic loss. This could be a…
Fixing Hardware Security Bugs with Large Language Models
Baleegh Ahmad, Shailja Thakur, Benjamin Tan +2
Novel AI-based code-writing Large Language Models (LLMs) such as OpenAI's Codex have demonstrated capabilities in many coding-adjacent domains. In this work we consider how LLMs ma…
A survey of Digital Manufacturing Hardware and Software Trojans
Prithwish Basu Roy, Mudit Bhargava, Chia-Yun Chang +4
Digital Manufacturing (DM) refers to the on-going adoption of smarter, more agile manufacturing processes and cyber-physical systems. This includes modern techniques and technologi…
Benchmarking Large Language Models for Automated Verilog RTL Code Generation
Shailja Thakur, Baleegh Ahmad, Zhenxing Fan +5
Automating hardware design could obviate a significant amount of human error from the engineering process and lead to fewer errors. Verilog is a popular hardware description langua…
Don't CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design
Baleegh Ahmad, Wei-Kai Liu, Luca Collini +9
To help prevent hardware security vulnerabilities from propagating to later design stages where fixes are costly, it is crucial to identify security concerns as early as possible,…
Lost at C: A User Study on the Security Implications of Large Language Model Code Assistants
Gustavo Sandoval, Hammond Pearce, Teo Nys +3
Large Language Models (LLMs) such as OpenAI Codex are increasingly being used as AI-based coding assistants. Understanding the impact of these tools on developers' code is paramoun…
High-Level Approaches to Hardware Security: A Tutorial
Hammond Pearce, Ramesh Karri, Benjamin Tan
Designers use third-party intellectual property (IP) cores and outsource various steps in the integrated circuit (IC) design and manufacturing flow. As a result, security vulnerabi…