203 citations · 677 across the 32 of their papers we have counts for
3 papers · 1 filter
AutoChip: Automating HDL Generation Using LLM Feedback
Shailja Thakur, Jason Blocklove, Hammond Pearce +3
Traditionally, designs are written in Verilog hardware description language (HDL) and debugged by hardware engineers. While this approach is effective, it is time-consuming and err…
VeriGen: A Large Language Model for Verilog Code Generation
Shailja Thakur, Baleegh Ahmad, Hammond Pearce +4
In this study, we explore the capability of Large Language Models (LLMs) to automate hardware design by generating high-quality Verilog code, a common language for designing and mo…
Benchmarking Large Language Models for Automated Verilog RTL Code Generation
Shailja Thakur, Baleegh Ahmad, Zhenxing Fan +5
Automating hardware design could obviate a significant amount of human error from the engineering process and lead to fewer errors. Verilog is a popular hardware description langua…