Protect Your Chip Design Intellectual Property: An Overview
arXiv:1902.05333 · doi:10.1145/3312614.3312657
Abstract
The increasing cost of integrated circuit (IC) fabrication has driven most companies to "go fabless" over time. The corresponding outsourcing trend gave rise to various attack vectors, e.g., illegal overproduction of ICs, piracy of the design intellectual property (IP), or insertion of hardware Trojans (HTs). These attacks are possibly conducted by untrusted entities residing all over the supply chain, ranging from untrusted foundries, test facilities, even to end-users. To overcome this multitude of threats, various techniques have been proposed over the past decade. In this paper, we review the landscape of IP protection techniques, which can be classified into logic locking, layout camouflaging, and split manufacturing. We discuss the history of these techniques, followed by state-of-the-art advancements, relevant limitations, and scope for future work.
arXiv commentINTERNATIONAL CONFERENCE ON OMNI-LAYER INTELLIGENT SYSTEMS (COINS), May 5--7, 2019, Crete, Greece; 6 pages, 3 figures, 1 table; [v2]: minor edits and update references, as in camera copy for COINS; [v3]: added ACM reference format and CCS concepts, minor edits
References in corpus (4)
- Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device- and Logic-Level Techniques
- SRCLock: SAT-Resistant Cyclic Logic Locking for Protecting the Hardware
- Raise Your Game for Split Manufacturing: Restoring the True Functionality Through BEOL
- Best of Both Worlds: Integration of Split Manufacturing and Camouflaging into a Security-Driven CAD Flow for 3D ICs
Cited by in corpus (6)
- Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging
- 2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets
- Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA
- A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects
- Hardware Security for and beyond CMOS Technology
- 3D Integration: Another Dimension Toward Hardware Security