52 citations · 600 across the 60 of their papers we have counts for
62 papers
Hardware Design and Security in the Era of Chiplets and LLMs
Johann Knechtel, Ozgur Sinanoglu, Paul V. Gratz +1
The semiconductor industry is undergoing a dual revolution: the shift toward heterogeneous 2.5D chiplet systems and the integration of Large Language Models (LLMs) into Electronic…
FinHardBench: Can LLMs Generate Latency-Aware Hardware for Financial Computing?
Weimin Fu, Hejia Zhang, Minghao Shao +6
Can large language models generate not just correct, but fast hardware? This paper investigates the question in financial FPGA design, where 5-10 nanoseconds of latency determines…
Security Analysis for SCONE Logic Locking
Akashdeep Saha, Mohammed Nabeel, Johann Knechtel +2
SCONE [DAC'25] expands a logic locking interface with additional encoded inputs derived from the original primary inputs, and admits two realizations: a \textit{with-ES} variant, w…
Leaking Circuit Secrets: Gradient Leakage Attacks on Graph Neural Networks
Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu
As graph neural networks (GNNs) become standard tools for critical tasks in circuit design and analysis, their security and privacy risks require careful attention. Here, we presen…
2.5D Root of Trust: Securing the Chiplet Ecosystem
Charles Williams, Mohammed Nabeel, Gino Chacon +3
The semiconductor industry is rapidly transitioning from monolithic systems-on-chip toward heterogeneous, multi-vendor 2.5D chiplet ecosystems integrated via silicon interposers. W…
LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges
Johann Knechtel, Ozgur Sinanoglu, Ramesh Karri
The integration of Large Language Models (LLMs) into Electronic Design Automation (EDA) and hardware security is rapidly reshaping the semiconductor industry. While LLMs offer unpr…
Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generation
Minghao Shao, Zeng Wang, Weimin Fu +5
Benchmarking of open-source LLMs for hardware design focuses on which LLMs to use, while treating inference-time decoding configuration as a secondary concern. This work shows that…
From Natural Language to Silicon: The Representation Bottleneck in LLM Hardware Design
Weimin Fu, Zeng Wang, Minghao Shao +5
Edge applications increasingly demand custom hardware, yet Field-Programmable Gate Array (FPGA) design requires expertise that domain engineers lack. Large Language Models (LLMs) p…
HarmChip: Evaluating Hardware Security Centric LLM Safety via Jailbreak Benchmarking
Zeng Wang, Minghao Shao, Weimin Fu +6
The integration of large language models (LLMs) into electronic design automation (EDA) workflows has introduced powerful capabilities for RTL generation, verification, and design…
VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog
Prithwish Basu Roy, Zeng Wang, Anatolii Chuvashlov +4
Large Language Models (LLMs) have shown significant improvement in RTL code generation. Despite the advances, the generated code is often riddled with common vulnerabilities and we…
GUIDE: GenAI Units In Digital Design Education
Weihua Xiao, Jason Blocklove, Matthew DeLorenzo +6
GenAI Units In Digital Design Education (GUIDE) is an open courseware repository with runnable Google Colab labs and other materials. We describe the repository's architecture and…
LLM4PQC - Accurate and Efficient Synthesis of PQC Cores by Feedback-Driven LLMs
Buddhi Perera, Zeng Wang, Weihua Xiao +4
The design of post-quantum cryptography (PQC) hardware is a complex and hierarchical process with many challenges. A primary bottleneck is the conversion of PQC reference codes fro…
Synthesis-in-the-Loop Evaluation of LLMs for RTL Generation: Quality, Reliability, and Failure Modes
Weimin Fu, Zeng Wang, Minghao Shao +5
RTL generation is more than code synthesis. Designs must be syntactically valid, synthesizable, correct, hardware-efficient. SOTA evaluations stop at functional correctness and do…
TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion
Saideep Sreekumar, Zeng Wang, Akashdeep Saha +6
Hardware Trojans (HTs) remain a critical threat because learning-based detectors often overfit to narrow trigger/payload patterns and small, stylized benchmarks. We introduce Troja…
Revisiting Logic Encryption
Rupesh Raj Karn, Lakshmi Likhitha Mankali, Zeng Wang +5
Modern circuits face various threats like reverse engineering, theft of intellectual property (IP), side-channel attacks, etc. Here, we present a novel approach for IP protection b…
TrojanLoC: LLM-based Framework for RTL Trojan Localization
Weihua Xiao, Zeng Wang, Minghao Shao +6
Hardware Trojans (HT s) are a persistent threat to integrated circuits, especially when inserted at the register-transfer level (RTL). Existing methods typically first convert the…
LockForge: Automating Paper-to-Code for Logic Locking with Multi-Agent Reasoning LLMs
Akashdeep Saha, Zeng Wang, Prithwish Basu Roy +3
Despite rapid progress in logic locking (LL), reproducibility remains a challenge as codes are rarely made public. We present LockForge, a first-of-its-kind, multi-agent large lang…
NetDeTox: Adversarial and Efficient Evasion of Hardware-Security GNNs via RL-LLM Orchestration
Zeng Wang, Minghao Shao, Akashdeep Saha +4
Graph neural networks (GNNs) have shown promise in hardware security by learning structural motifs from netlist graphs. However, this reliance on motifs makes GNNs vulnerable to ad…
Large Language Models (LLMs) for Electronic Design Automation (EDA)
Kangwei Xu, Denis Schwachhofer, Jason Blocklove +10
With the growing complexity of modern integrated circuits, hardware engineers are required to devote more effort to the full design-to-manufacturing workflow. This workflow involve…
Targeted Wearout Attacks in Microprocessor Cores
Joshua Mashburn, Johann Knechtel, Florian Klemme +3
Negative-Bias Temperature Instability is a dominant aging mechanism in nanoscale CMOS circuits such as microprocessors. With this aging mechanism, the rate of device aging is depen…
VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code
Raghu Vamshi Hemadri, Jitendra Bhandari, Andre Nakkab +5
Modern chip design is complex, and there is a crucial need for early-stage prediction of key design-quality metrics like timing and routing congestion directly from Verilog code (a…
SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Design
Zeng Wang, Minghao Shao, Rupesh Karn +6
Large Language Models (LLMs) offer transformative capabilities for hardware design automation, particularly in Verilog code generation. However, they also pose significant data sec…
Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form
Prithwish Basu Roy, Akashdeep Saha, Manaar Alam +4
Automated Verilog code synthesis poses significant challenges and typically demands expert oversight. Traditional high-level synthesis (HLS) methods often fail to scale for real-wo…
VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination
Zeng Wang, Minghao Shao, Jitendra Bhandari +5
Large Language Models (LLMs) have revolutionized code generation, achieving exceptional results on various established benchmarking frameworks. However, concerns about data contami…