activity
20172026
most citedObfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging

52 citations · 600 across the 60 of their papers we have counts for

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Showing cs.LGShow all

5 papers · 1 filter

cs.LG2026

Leaking Circuit Secrets: Gradient Leakage Attacks on Graph Neural Networks

Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu

As graph neural networks (GNNs) become standard tools for critical tasks in circuit design and analysis, their security and privacy risks require careful attention. Here, we presen…

cs.LG2025★ 1 cited

SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Design

Zeng Wang, Minghao Shao, Rupesh Karn +6

Large Language Models (LLMs) offer transformative capabilities for hardware design automation, particularly in Verilog code generation. However, they also pose significant data sec…

cs.LG2024

LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust

Zeng Wang, Lilas Alrahis, Likhitha Mankali +2

Chip design is about to be revolutionized by the integration of large language, multimodal, and circuit models (collectively LxMs). While exploring this exciting frontier with trem…

cs.LG2022★ 3 cited

Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs

Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu

Graph neural networks (GNNs) have pushed the state-of-the-art (SOTA) for performance in learning and predicting on large-scale data present in social networks, biology, etc. Since…

cs.LG2022★ 4 cited

GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation

Lilas Alrahis, Johann Knechtel, Florian Klemme +2

Process variations and device aging impose profound challenges for circuit designers. Without a precise understanding of the impact of variations on the delay of circuit paths, gua…