52 citations · 600 across the 60 of their papers we have counts for
6 papers · 1 filter
RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation
Lakshmi Likhitha Mankali, Jitendra Bhandari, Manaar Alam +4
Large language models (LLMs) have demonstrated remarkable potential with code generation/completion tasks for hardware design. In fact, LLM-based hardware description language (HDL…
ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search
Jitendra Bhandari, Animesh Basak Chowdhury, Mohammed Nabeel +4
Power side-channel (PSC) analysis is pivotal for securing cryptographic hardware. Prior art focused on securing gate-level netlists obtained as-is from chip design automation, negl…
LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines
Jitendra Bhandari, Johann Knechtel, Ramesh Narayanaswamy +2
This work investigates the potential of tailoring Large Language Models (LLMs), specifically GPT3.5 and GPT4, for the domain of chip testing. A key aspect of chip design is functio…
LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust
Zeng Wang, Lilas Alrahis, Likhitha Mankali +2
Chip design is about to be revolutionized by the integration of large language, multimodal, and circuit models (collectively LxMs). While exploring this exciting frontier with trem…
TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans
Fangzhou Wang, Qijing Wang, Lilas Alrahis +7
Due to cost benefits, supply chains of integrated circuits (ICs) are largely outsourced nowadays. However, passing ICs through various third-party providers gives rise to many secu…
Lightweight Countermeasures Against Static Power Side-Channel Attacks
Jitendra Bhandari, Mohammed Nabeel, Likhitha Mankali +3
This paper presents a novel defense strategy against static power side-channel attacks (PSCAs), a critical threat to cryptographic security. Our method is based on (1) carefully tu…