activity
20172026
most citedObfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging

52 citations · 600 across the 60 of their papers we have counts for

collaborators
Showing 2022Show all

5 papers · 1 filter

cs.LG2022★ 3 cited

Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs

Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu

Graph neural networks (GNNs) have pushed the state-of-the-art (SOTA) for performance in learning and predicting on large-scale data present in social networks, biology, etc. Since…

cs.CR2022

X-Volt: Joint Tuning of Driver Strengths and Supply Voltages Against Power Side-Channel Attacks

Saideep Sreekumar, Mohammed Ashraf, Mohammed Nabeel +2

Power side-channel (PSC) attacks are well-known threats to sensitive hardware like advanced encryption standard (AES) crypto cores. Given the significant impact of supply voltages…

cs.CR2022★ 1 cited

Security Closure of IC Layouts Against Hardware Trojans

Fangzhou Wang, Qijing Wang, Bangqi Fu +7

Due to cost benefits, supply chains of integrated circuits (ICs) are largely outsourced nowadays. However, passing ICs through various third-party providers gives rise to many thre…

cs.CR2022★ 1 cited

Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems

Gino A. Chacon, Charles Williams, Johann Knechtel +2

As industry moves toward chiplet-based designs, the insertion of hardware Trojans poses a significant threat to the security of these systems. These systems rely heavily on cache c…

cs.LG2022★ 4 cited

GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation

Lilas Alrahis, Johann Knechtel, Florian Klemme +2

Process variations and device aging impose profound challenges for circuit designers. Without a precise understanding of the impact of variations on the delay of circuit paths, gua…