30 citations · 61 across the 4 of their papers we have counts for
4 papers
Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain Access
Nimisha Limaye, Abhrajit Sengupta, Mohammed Nabeel +1
The security of logic locking has been called into question by various attacks, especially a Boolean satisfiability (SAT) based attack, that exploits scan access in a working chip.…
An Interposer-Based Root of Trust: Seize the Opportunity for Secure System-Level Integration of Untrusted Chiplets
Mohammed Nabeel, Mohammed Ashraf, Satwik Patnaik +3
Leveraging 2.5D interposer technology, we advocate the integration of untrusted commodity components/chiplets with physically separate, entrusted logic components. Such organizatio…
Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging
Satwik Patnaik, Mohammed Ashraf, Johann Knechtel +1
Layout camouflaging (LC) is a promising technique to protect chip design intellectual property (IP) from reverse engineers. Most prior art, however, cannot leverage the full potent…
Rethinking Split Manufacturing: An Information-Theoretic Approach with Secure Layout Techniques
Abhrajit Sengupta, Satwik Patnaik, Johann Knechtel +3
Split manufacturing is a promising technique to defend against fab-based malicious activities such as IP piracy, overbuilding, and insertion of hardware Trojans. However, a network…