activity
20172023
most citedObfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging

52 citations · 584 across the 43 of their papers we have counts for

collaborators
Showing 2018Show all

5 papers · 1 filter

cs.CR2018★ 17 cited

Best of Both Worlds: Integration of Split Manufacturing and Camouflaging into a Security-Driven CAD Flow for 3D ICs

Satwik Patnaik, Mohammed Ashraf, Ozgur Sinanoglu +1

With the globalization of manufacturing and supply chains, ensuring the security and trustworthiness of ICs has become an urgent challenge. Split manufacturing (SM) and layout camo…

cs.CR2018★ 36 cited

Opening the Doors to Dynamic Camouflaging: Harnessing the Power of Polymorphic Devices

Nikhil Rangarajan, Satwik Patnaik, Johann Knechtel +3

The era of widespread globalization has led to the emergence of hardware-centric security threats throughout the IC supply chain. Prior defenses like logic locking, layout camoufla…

cs.CR2018★ 21 cited

Raise Your Game for Split Manufacturing: Restoring the True Functionality Through BEOL

Satwik Patnaik, Mohammed Ashraf, Johann Knechtel +1

Split manufacturing (SM) seeks to protect against piracy of intellectual property (IP) in chip designs. Here we propose a scheme to manipulate both placement and routing in an inte…

cs.CR2018★ 45 cited

Advancing Hardware Security Using Polymorphic and Stochastic Spin-Hall Effect Devices

Satwik Patnaik, Nikhil Rangarajan, Johann Knechtel +2

Protecting intellectual property (IP) in electronic circuits has become a serious challenge in recent years. Logic locking/encryption and layout camouflaging are two prominent tech…

cs.CR2018★ 23 cited

Concerted Wire Lifting: Enabling Secure and Cost-Effective Split Manufacturing

Satwik Patnaik, Johann Knechtel, Mohammed Ashraf +1

Here we advance the protection of split manufacturing (SM)-based layouts through the judicious and well-controlled handling of interconnects. Initially, we explore the cost-securit…