Hardware Security for and beyond CMOS Technology
arXiv:2001.08780 · doi:10.1145/3439706.3446902
Abstract
As with most aspects of electronic systems and integrated circuits, hardware security has traditionally evolved around the dominant CMOS technology. However, with the rise of various emerging technologies, whose main purpose is to overcome the fundamental limitations for scaling and power consumption of CMOS technology, unique opportunities arise also to advance the notion of hardware security. In this paper, I first provide an overview on hardware security in general. Next, I review selected emerging technologies, namely (i) spintronics, (ii) memristors, (iii) carbon nanotubes and related transistors, (iv) nanowires and related transistors, and (v) 3D and 2.5D integration. I then discuss their application to advance hardware security and also outline related challenges.
[v1] ISPD'20; [v2] extended arXiv version; [v3] some references updated, some paragraphs further extended; [v4] ISPD'21, extended arXiv version
References in corpus (14)
- Graphene Spintronics
- Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device- and Logic-Level Techniques
- Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging
- ZombieLoad: Cross-Privilege-Boundary Data Sampling
- 2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets
- UNSAIL: Thwarting Oracle-Less Machine Learning Attacks on Logic Locking
- Logic Locking for Secure Outsourced Chip Fabrication: A New Attack and Provably Secure Defense Mechanism
- Interdiction in Practice -- Hardware Trojan Against a High-Security USB Flash Drive
- Rethinking Split Manufacturing: An Information-Theoretic Approach with Secure Layout Techniques
- Protect Your Chip Design Intellectual Property: An Overview
- Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime
- Power Side-Channel Attacks in Negative Capacitance Transistor (NCFET)
- Real-World Snapshots vs. Theory: Questioning the t-Probing Security Model
- An Interposer-Based Root of Trust: Seize the Opportunity for Secure System-Level Integration of Untrusted Chiplets