Characterization of a Serializer ASIC chip for the upgrade of the ATLAS muon detector

Abstract

We report on the design of a serializer ASIC to be used in the ATLAS forward muon detector for trigger data transmission. We discuss the performance of a prototype chip covering power dissipation, latency and stable operating line rate. Tests show that the serializer is capable of running at least at 5.76 Gbps with a bit error ratio below 1x10^{-15}, and a power consumption of 200 mW running at 4.8 Gbps. The latency between the start of loading 30 bits into the serializer to the transmission of the first bit from the serializer is measured to be about 6 ns.

7 pages, 8 figures, accepted by IEEE-Transactions on Nuclear Science

References in corpus (2)

• Observation of a new particle in the search for the Standard Model Higgs boson with the ATLAS detector at the LHC
• Observation of a new boson at a mass of 125 GeV with the CMS experiment at the LHC

Cited by in corpus (9)

• FPGA Implementation of a Fixed Latency Scheme in a Signal Packet Router for the Upgrade of ATLAS Forward Muon Trigger Electronics
• Design of a Trigger Data Serializer ASIC for the Upgrade of the ATLAS Forward Muon Spectrometer
• The New Small Wheel electronics
• A Low-Power, Low-Latency, Dual-Channel Serializer ASIC for Detector Front-End Readout
• LOCx2-130, a low-power, low-latency, 2 x 4.8-Gbps serializer ASIC for detector front-end readout
• Two low-power optical data transmission ASICs for the ATLAS Liquid Argon Calorimeter readout upgrade
• The Latency Validation of the Optical Link for the ATLAS Liquid Argon Calorimeter Phase-I Trigger Upgrade
• Mass Production of a Trigger Data Serializer ASIC for the Upgrade of the Muon Spectrometer at the ATLAS Experiment
• Design and testing of an sTGC ASIC interface board for the ATLAS New Small Wheel upgrade