The Latency Validation of the Optical Link for the ATLAS Liquid Argon Calorimeter Phase-I Trigger Upgrade

Abstract

Two optical data link data transmission Application Specific Integrated Circuits (ASICs), the baseline and its backup, have been designed for the ATLAS Liquid Argon (LAr) Calorimeter Phase-I trigger upgrade. The latency of each ASIC and that of its corresponding receiver implemented in a back-end Field-Programmable Gate Array (FPGA) are critical specifications. In this paper, we present the latency measurements and simulation of two ASICs. The measurement results indicate that both ASICs achieve their design goals and meet the latency specifications. The consistency between the simulation and measurements validates the ASIC latency characterization.

References in corpus (3)

• LOCx2, a Low-latency, Low-overhead, 2 x 5.12-Gbps Transmitter ASIC for the ATLAS Liquid Argon Calorimeter Trigger Upgrade
• A line code with quick-resynchronization capability and low latency for the optical data links of LHC experiments
• A Low-Power, Low-Latency, Dual-Channel Serializer ASIC for Detector Front-End Readout

Cited by in corpus (1)

• The Phase-I Trigger Readout Electronics Upgrade of the ATLAS Liquid Argon Calorimeters