A Low-Power, Low-Latency, Dual-Channel Serializer ASIC for Detector Front-End Readout
arXiv:2009.07130 · doi:10.1088/1748-0221/12/01/C01049
Abstract
In this paper, we present a dual-channel serializer ASIC, LOCx2, and its pin-compatible backup, LOCx2-130, for detector front-end readout. LOCx2 is fabricated in a 0.25-um Silicon-on-Sapphire CMOS process and each channel operates at 5.12 Gbps, while LOCx2-130 is fabricated in a 130-nm bulk CMOS process and each channel operates at 4.8 Gbps. The power consumption and the transmission latency are 900 mW and 27 ns for LOCx2 and the corresponding simulation result of LOCx2-130 are 386 mW and 38 ns, respectively.
arXiv comment8 pages, 10 figures
References in corpus (5)
- A Radiation-Hard Dual Channel 4-bit Pipeline for a 12-bit 40 MS/s ADC Prototype with extended Dynamic Range for the ATLAS Liquid Argon Calorimeter Readout Electronics Upgrade at the CERN LHC
- Characterization of a Serializer ASIC chip for the upgrade of the ATLAS muon detector
- Evaluation of commercial ADC radiation tolerance for accelerator experiments
- Mid-board miniature dual channel optical transmitter MTx and transceiver MTRx
- LOCx2, a Low-latency, Low-overhead, 2 x 5.12-Gbps Transmitter ASIC for the ATLAS Liquid Argon Calorimeter Trigger Upgrade