FPGA Implementation of a Fixed Latency Scheme in a Signal Packet Router for the Upgrade of ATLAS Forward Muon Trigger Electronics

Abstract

We propose a new fixed latency scheme for Xilinx gigabit transceivers that will be used in the upgrade of the ATLAS forward muon spectrometer at the Large Hadron Collider. The fixed latency scheme is implemented in a 4.8 Gbps link between a frontend data serializer ASIC and a packet router. To achieve fixed latency, we use IO delay and dedicated carry in resources in a Xilinx FPGA, while minimally relying on the embedded features of the FPGA transceivers. The scheme is protocol independent and can be adapted to FPGA from other vendors with similar resources. This paper presents a detailed implementation of the fixed latency scheme, as well as simulations of the real environment in the ATLAS forward muon region.

8 pages, 8 figures, accepted by IEEE - Transactions on Nuclear Science

References in corpus (1)

• Characterization of a Serializer ASIC chip for the upgrade of the ATLAS muon detector

Cited by in corpus (5)

• Design of a Trigger Data Serializer ASIC for the Upgrade of the ATLAS Forward Muon Spectrometer
• A Multi-Layer SEU Mitigation Strategy to Improve FPGA Design Robustness for the ATLAS Muon Spectrometer Upgrade
• The New Small Wheel electronics
• Mass Production of a Trigger Data Serializer ASIC for the Upgrade of the Muon Spectrometer at the ATLAS Experiment
• Design and testing of an sTGC ASIC interface board for the ATLAS New Small Wheel upgrade