Extrinsic and Intrinsic Charge Trapping at the Graphene/Ferroelectric Interface

Abstract

The interface between graphene and the ferroelectric superlattice $\mathrm{PbTi}{\mathrm{O}}_3/SrTi{\mathrm{O}}_3$ (PTO/STO) is studied. Tuning the transition temperature through the PTO/STO volume fraction minimizes the adsorbates at the graphene-ferroelectric interface, allowing robust ferroelectric hysteresis to be demonstrated. Intrinsic charge traps from the ferroelectric surface defects can adversely affect the graphene channel hysteresis, and can be controlled by careful sample processing, enabling systematic study of the charge trapping mechanism.

25 pages, 5 figures. Published online in Nano letters, Article ASAP, August 18, 2014, http://pubs.acs.org/doi/abs/10.1021/nl502669v

References in corpus (8)

• Realization of a High Mobility Dual-gated Graphene Field Effect Transistor with Al2O3 Dielectric
• Gate-controlled non-volatile graphene-ferroelectric memory
• Graphene field effect transistors with ferroelectric gating
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• High-Mobility Few-Layer Graphene Field Effect Transistors Fabricated on Epitaxial Ferroelectric Gate Oxides
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Cited by in corpus (6)

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• Graphene magnetoresistance control by photoferroelectric substrate
• Strain engineering of ferromagnetic-graphene-ferroelectric nanostructures
• Graphene separation and stretching induced by piezoelectric effect of ferroelectric domains: impact on the conductance of graphene channel
• Ferroelectric hysteresis in singly aligned graphene-hBN moiré superlattices
• Chemical control of polymorphism and ferroelectricity in PbTiO3 and SrTiO3 monolayers and bilayers