89 citations · 182 across the 26 of their papers we have counts for
26 papers
DC: Depth Control on Quantum Classical Circuit
Movahhed Sadeghi, Soheil Khadirsharbiyani, Mostafa Eghbali Zarch +1
The growing prevalence of near-term intermediate-scale quantum (NISQ) systems has brought forth a heightened focus on the issue of circuit reliability. Several quantum computing ac…
Quantum Circuit Resizing
Movahhed Sadeghi, Soheil Khadirsharbiyani, Mahmut Taylan Kandemir
Existing quantum systems provide very limited physical qubit counts, trying to execute a quantum algorithm/circuit on them that have a higher number of logical qubits than physical…
Revamping Storage Class Memory With Hardware Automated Memory-Over-Storage Solution
Jie Zhang, Miryeong Kwon, Donghyun Gouk +4
Large persistent memories such as NVDIMM have been perceived as a disruptive memory technology, because they can maintain the state of a system even after a power failure and allow…
GraphGuess: Approximate Graph Processing System with Adaptive Correction
Morteza Ramezani, Mahmut T. Kandemir, Anand Sivasubramaniam
Graph-based data structures have drawn great attention in recent years. The large and rapidly growing trend on developing graph processing systems focuses mostly on improving the p…
Fifer: Tackling Underutilization in the Serverless Era
Jashwant Raj Gunasekaran, Prashanth Thinakaran, Nachiappan Chidambaram +2
Datacenters are witnessing a rapid surge in the adoption of serverless functions for microservices-based applications. A vast majority of these microservices typically span less th…
Towards Designing a Self-Managed Machine Learning Inference Serving System inPublic Cloud
Jashwant Raj Gunasekaran, Prashanth Thinakaran, Cyan Subhra Mishra +2
We are witnessing an increasing trend towardsusing Machine Learning (ML) based prediction systems, span-ning across different application domains, including productrecommendation s…
Multiverse: Dynamic VM Provisioning for Virtualized High Performance Computing Clusters
Jashwant Raj Gunasekaran, Michael Cui, Prashanth Thinakaran +3
Traditionally, HPC workloads have been deployed in bare-metal clusters; but the advances in virtualization have led the pathway for these workloads to be deployed in virtualized cl…
FastDrain: Removing Page Victimization Overheads in NVMe Storage Stack
Jie Zhang, Miryeong Kwon, Sanghyun Han +3
Host-side page victimizations can easily overflow the SSD internal buffer, which interferes I/O services of diverse user applications thereby degrading user-level experiences. To a…
AMOEBA: A Coarse Grained Reconfigurable Architecture for Dynamic GPU Scaling
Xianwei Cheng, Hui Zhao, Mahmut Kandemir +2
Different GPU applications exhibit varying scalability patterns with network-on-chip (NoC), coalescing, memory and control divergence, and L1 cache behavior. A GPU consists of seve…
Alleviating Bottlenecks for DNN Execution on GPUs via Opportunistic Computing
Xianwei Cheng, Hui Zhao, Mahmut Kandemir +2
Edge computing and IoT applications are severely constrained by limited hardware resource. This makes memory consuming DNN frameworks not applicable to edge computing. Simple algor…
On a caching system with object sharing
George Kesidis, Nader Alfares, Xi Li +3
We consider a content-caching system thatis shared by a number of proxies. The cache could belocated in an edge-cloud datacenter and the proxies couldeach serve a large population…
FUSE: Fusing STT-MRAM into GPUs to Alleviate Off-Chip Memory Access Overheads
Jie Zhang, Myoungsoo Jung, Mahmut Taylan Kandemir
In this work, we propose FUSE, a novel GPU cache system that integrates spin-transfer torque magnetic random-access memory (STT-MRAM) into the on-chip L1D cache. FUSE can minimize…
Amber: Enabling Precise Full-System Simulation with Detailed Modeling of All SSD Resources
Donghyun Gouk, Miryeong Kwon, Jie Zhang +5
SSDs become a major storage component in modern memory hierarchies, and SSD research demands exploring future simulation-based studies by integrating SSD subsystems into a full-sys…
Architectural exploration of heterogeneous memory systems
M. Horro, G. Rodríguez, J. Touriño +1
Heterogeneous systems appear as a viable design alternative for the dark silicon era. In this paradigm, a processor chip includes several different technological alternatives for i…
Holistic Management of the GPGPU Memory Hierarchy to Manage Warp-level Latency Tolerance
Rachata Ausavarungnirun, Saugata Ghose, Onur Kayıran +4
In a modern GPU architecture, all threads within a warp execute the same instruction in lockstep. For a memory instruction, this can lead to memory divergence: the memory requests…
TraceTracker: Hardware/Software Co-Evaluation for Large-Scale I/O Workload Reconstruction
Miryeong Kwon, Jie Zhang, Gyuyoung Park +5
Block traces are widely used for system studies, model verifications, and design analyses in both industry and academia. While such traces include detailed block access patterns, e…
Sprinkler: Maximizing Resource Utilization in Many-Chip Solid State Disks
Myoungsoo Jung, Mahmut T. Kandemir
Resource utilization is one of the emerging problems in many-chip SSDs. In this paper, we propose Sprinkler, a novel device-level SSD controller, which targets maximizing resource…
SimpleSSD: Modeling Solid State Drives for Holistic System Simulation
Myoungsoo Jung, Jie Zhang, Ahmed Abulila +5
Existing solid state drive (SSD) simulators unfortunately lack hardware and/or software architecture models. Consequently, they are far from capturing the critical features of cont…
Exploiting Data Longevity for Enhancing the Lifetime of Flash-based Storage Class Memory
Wonil Choi, Mohammad Arjomand, Myoungsoo Jung +1
Storage-class memory (SCM) combines the benefits of a solid-state memory, such as high-performance and robustness, with the archival capabilities and low cost of conventional hard-…
A Study on Performance and Power Efficiency of Dense Non-Volatile Caches in Multi-Core Systems
Amin Jadidi, Mohammad Arjomand, Mahmut T. Kandemir +1
In this paper, we present a novel cache design based on Multi-Level Cell Spin-Transfer Torque RAM (MLC STTRAM) that can dynamically adapt the set capacity and associativity to use…
A Framework for Accelerating Bottlenecks in GPU Execution with Assist Warps
Nandita Vijaykumar, Gennady Pekhimenko, Adwait Jog +7
Modern Graphics Processing Units (GPUs) are well provisioned to support the concurrent execution of thousands of threads. Unfortunately, different bottlenecks during execution and…
A Constraint Network Based Approach to Memory Layout Optimization
G. Chen, M. Kandemir, M. Karakoy
While loop restructuring based code optimization for array intensive applications has been successful in the past, it has several problems such as the requirement of checking depen…
Access Pattern-Based Code Compression for Memory-Constrained Embedded Systems
O. Ozturk, H. Saputra, M. Kandemir +1
As compared to a large spectrum of performance optimizations, relatively little effort has been dedicated to optimize other aspects of embedded applications such as memory space re…
Reliability-Centric High-Level Synthesis
S. Tosun, N. Mansouri, E. Arvas +2
Importance of addressing soft errors in both safety critical applications and commercial consumer products is increasing, mainly due to ever shrinking geometries, higher-density ci…