89 citations · 105 across the 12 of their papers we have counts for
7 papers · 1 filter
Revamping Storage Class Memory With Hardware Automated Memory-Over-Storage Solution
Jie Zhang, Miryeong Kwon, Donghyun Gouk +4
Large persistent memories such as NVDIMM have been perceived as a disruptive memory technology, because they can maintain the state of a system even after a power failure and allow…
AMOEBA: A Coarse Grained Reconfigurable Architecture for Dynamic GPU Scaling
Xianwei Cheng, Hui Zhao, Mahmut Kandemir +2
Different GPU applications exhibit varying scalability patterns with network-on-chip (NoC), coalescing, memory and control divergence, and L1 cache behavior. A GPU consists of seve…
FUSE: Fusing STT-MRAM into GPUs to Alleviate Off-Chip Memory Access Overheads
Jie Zhang, Myoungsoo Jung, Mahmut Taylan Kandemir
In this work, we propose FUSE, a novel GPU cache system that integrates spin-transfer torque magnetic random-access memory (STT-MRAM) into the on-chip L1D cache. FUSE can minimize…
Amber: Enabling Precise Full-System Simulation with Detailed Modeling of All SSD Resources
Donghyun Gouk, Miryeong Kwon, Jie Zhang +5
SSDs become a major storage component in modern memory hierarchies, and SSD research demands exploring future simulation-based studies by integrating SSD subsystems into a full-sys…
Architectural exploration of heterogeneous memory systems
M. Horro, G. Rodríguez, J. Touriño +1
Heterogeneous systems appear as a viable design alternative for the dark silicon era. In this paradigm, a processor chip includes several different technological alternatives for i…
Holistic Management of the GPGPU Memory Hierarchy to Manage Warp-level Latency Tolerance
Rachata Ausavarungnirun, Saugata Ghose, Onur Kayıran +4
In a modern GPU architecture, all threads within a warp execute the same instruction in lockstep. For a memory instruction, this can lead to memory divergence: the memory requests…