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20072026
most citedUnsupervised Heart-rate Estimation in Wearables With Liquid States and A Probabilistic Readout

89 citations · 180 across the 30 of their papers we have counts for

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Showing cs.ARShow all

6 papers · 1 filter

cs.AR2025

Optimizing GEMM for Energy and Performance on Versal ACAP Architectures

Ilias Papalamprou, Dimosthenis Masouros, Ioannis Loudaros +2

General Matrix Multiplication (GEMM) is a fundamental operation in many scientific workloads, signal processing, and particularly deep learning. It is often a bottleneck for perfor…

cs.AR2022

A Soft SIMD Based Energy Efficient Computing Microarchitecture

Pengbo Yu, Alexandre Levisse, Mohit Gupta +4

The ever-increasing size and computational complexity of today's machine-learning algorithms pose an increasing strain on the underlying hardware. In this light, novel and dedicate…

cs.AR2022★ 2 cited

VWR2A: A Very-Wide-Register Reconfigurable-Array Architecture for Low-Power Embedded Devices

Benoît Walter Denkinger, Miguel Peón-Quirós, Mario Konijnenburg +2

Edge-computing requires high-performance energy-efficient embedded systems. Fixed-function or custom accelerators, such as FFT or FIR filter engines, are very efficient at implemen…

cs.AR2021★ 9 cited

MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration

Matheus Cavalcante, Anthony Agnesina, Samuel Riedel +6

Three-dimensional integrated circuits promise power, performance, and footprint gains compared to their 2D counterparts, thanks to drastic reductions in the interconnects' length t…

cs.AR2007

A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware

Javier Resano, Daniel Mozos, Francky Catthoor

Due to the emergence of highly dynamic multimedia applications there is a need for flexible platforms and run-time scheduling support for embedded systems. Dynamic Reconfigurable H…

cs.AR2007

A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck

Minas Dasygenis, Erik Brockmeyer, Bart Durinck +3

The memory subsystem has always been a bottleneck in performance as well as significant power contributor in memory intensive applications. Many researchers have presented multi-la…