6 papers
Architectural Classification of XR Workloads: Cross-Layer Archetypes and Implications
Xinyu Shi, Simei Yang, Francky Catthoor
Edge and mobile platforms for augmented and virtual reality, collectively referred to as extended reality (XR) must deliver deterministic ultra-low-latency performance under string…
Scenario-Aware Control of Segmented Ladder Bus: Design and FPGA Implementation
Phu Khanh Huynh, Francky Catthoor, Anup Das
Large-scale neuromorphic architectures consist of computing tiles that communicate spikes using a shared interconnect. The communication patterns in these systems are inherently sp…
PIMfused: Near-Bank DRAM-PIM with Fused-layer Dataflow for CNN Data Transfer Optimization
Simei Yang, Xinyu Shi, Lu Zhao +3
Near-bank Processing-in-Memory (PIM) architectures integrate processing cores (PIMcores) close to DRAM banks to mitigate the high cost of off-chip memory accesses. When acceleratin…
Mapping and Scheduling Spiking Neural Networks On Segmented Ladder Bus Architectures
Phu Khanh Huynh, Francky Catthoor, Anup Das
Large-scale neuromorphic architectures consist of computing tiles that communicate spikes using a shared interconnect. The communication patterns in such systems are inherently spa…
Addressing memory bandwidth scalability in vector processors for streaming applications
Jordi Altayo, Paul Delestrac, David Novo +3
As the size of artificial intelligence and machine learning (AI/ML) models and datasets grows, the memory bandwidth becomes a critical bottleneck. The paper presents a novel extend…
Calibrating DRAMPower Model for HPC: A Runtime Perspective from Real-Time Measurements
Xinyu Shi, Dina Ali Abdelhamid, Thomas Ilsche +4
Main memory's rising energy consumption has emerged as a critical challenge in modern computing architectures, particularly in large-scale systems, driven by frequent access patter…