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20122023
most citedA simple 1-byte 1-clock RC4 design and its efficient implementation in FPGA coprocessor for secured ethernet communication

6 citations · 25 across the 17 of their papers we have counts for

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Showing 2021Show all

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cs.AR2021

Towards Power Efficient DNN Accelerator Design on Reconfigurable Platform

Rourab Paul, Sreetama Sarkar, Suman Sau +3

The exponential emergence of Field Programmable Gate Array (FPGA) has accelerated the research of hardware implementation of Deep Neural Network (DNN). Among all DNN processors, do…