activity
20122023
most citedA simple 1-byte 1-clock RC4 design and its efficient implementation in FPGA coprocessor for secured ethernet communication

6 citations · 25 across the 17 of their papers we have counts for

collaborators
Showing 2015Show all

1 paper · 1 filter

cs.AR2015

A Novel Method for Soft Error Mitigation in FPGA using Adaptive Cross Parity Code

Swagata Mandal, Rourab Paul, Suman Sau +2

Field Programmable Gate Arrays (FPGAs) are more prone to be affected by transient faults in presence of radiation and other environmental hazards compared to Application Specific I…