6 citations · 25 across the 17 of their papers we have counts for
18 papers
Power Aware Scheduling of Tasks on FPGAs in Data Centers
Rourab Paul, Marco Danelutto
A variety of computing platform like Field Programmable Gate Array (FPGA), Graphics Processing Unit (GPU) and multicore Central Processing Unit (CPU) in data centers are suitable f…
Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Post Quantum Cryptography on Reconfigurable Architecture
Paresh Baidya, Swagata Mondal, Rourab Paul
Ring Learning With Error (RLWE) algorithm is used in Post Quantum Cryptography (PQC) and Homomorphic Encryption (HE) algorithm. The existing classical crypto algorithms may be brok…
Smart Contract Assisted Blockchain based PKI System
Amrutanshu Panigrahi, Ajit Kumar Nayak, Rourab Paul
The proposed smart contract can prevent seven cyber attacks, such as Denial of Service (DoS), Man in the Middle Attack (MITM), Distributed Denial of Service (DDoS), 51\%, Injection…
Towards Power Efficient DNN Accelerator Design on Reconfigurable Platform
Rourab Paul, Sreetama Sarkar, Suman Sau +3
The exponential emergence of Field Programmable Gate Array (FPGA) has accelerated the research of hardware implementation of Deep Neural Network (DNN). Among all DNN processors, do…
The Blockchain Based Auditor on Secret key Life Cycle in Reconfigurable Platform
Rourab Paul, Nimisha Ghosh, Amlan Chakrabarti +1
The growing sophistication of cyber attacks, vulnerabilities in high computing systems and increasing dependency on cryptography to protect our digital data make it more important…
iDCR: Improved Dempster Combination Rule for Multisensor Fault Diagnosis
Nimisha Ghosh, Sayantan Saha, Rourab Paul
Data gathered from multiple sensors can be effectively fused for accurate monitoring of many engineering applications. In the last few years, one of the most sought after applicati…
IoT based Smart Access Controlled Secure Smart City Architecture Using Blockchain
Rourab Paul, Nimisha Ghosh, Suman Sau +2
Standard security protocols like SSL, TLS, IPSec etc. have high memory and processor consumption which makes all these security protocols unsuitable for resource constrained platfo…
Fault Matters: Sensor Data Fusion for Detection of Faults using Dempster-Shafer Theory of Evidence in IoT-Based Applications
Nimisha Ghosh, Rourab Paul, Satyabrata Maity +2
Fault detection in sensor nodes is a pertinent issue that has been an important area of research for a very long time. But it is not explored much as yet in the context of Internet…
Accelerating More Secure RC4 : Implementation of Seven FPGA Designs in Stages upto 8 byte per clock
Rourab Paul, Hemanta Dey, Amlan Chakrabarti +1
RC4 can be made more secured if an additional RC4-like Post-KSA Random Shuffing (PKRS) process is introduced between KSA and PRGA. It can also be made significantly faster if RC4 b…
A Novel Method for Soft Error Mitigation in FPGA using Adaptive Cross Parity Code
Swagata Mandal, Rourab Paul, Suman Sau +2
Field Programmable Gate Arrays (FPGAs) are more prone to be affected by transient faults in presence of radiation and other environmental hazards compared to Application Specific I…
Multi Core SSL/TLS Security Processor Architecture Prototype Design with automated Preferential Algorithm in FPGA
Rourab Paul, Amlan Chakrabarti, Ranjan Ghosh
In this paper a pipelined architecture of a high speed network security processor (NSP) for SSL,TLS protocol is implemented on a system on chip (SOC) where hardware information of…
Performance Evaluation of ECC in Single and Multi Processor Architectures on FPGA Based Embedded System
Sruti Agarwal, Sangeet Saha, Rourab Paul +1
Cryptographic algorithms are computationally costly and the challenge is more if we need to execute them in resource constrained embedded systems. Field Programmable Gate Arrays (F…
Fault Detection for RC4 Algorithm and its Implementation on FPGA Platform
Rourab Paul, Amlan Chakrabarti, Ranjan Ghosh
In hardware implementation of a cryptographic algorithm, one may achieve leakage of secret information by creating scopes to introduce controlled faulty bit(s) even though the algo…
Hardware Implementation of four byte per clock RC4 algorithm
Rourab Paul, Amlan Chakrabarti, Ranjan Ghosh
In the field of cryptography till date the 2-byte in 1-clock is the best known RC4 hardware design [1], while 1-byte in 1-clock [2], and the 1-byte in 3 clocks [3][4] are the best…
A brief experience on journey through hardware developments for image processing and its applications on Cryptography
Sangeet Saha, Chandrajit pal, Rourab paul +2
The importance of embedded applications on image and video processing,communication and cryptography domain has been taking a larger space in current research era. Improvement of p…
Architecture for real time continuous sorting on large width data volume for fpga based applications
Rourab Paul, Suman Sau, Amlan Chakrabarti
In engineering applications sorting is an important and widely studied problem where execution speed and resources used for computation are of extreme importance, especially if we…
Design and implementation of real time AES-128 on real time operating system for multiple FPGA communication
Rourab Paul, Sangeet Saha, Suman Sau +1
Security is the most important part in data communication system, where more randomization in secret keys increases the security as well as complexity of the cryptography algorithm…
A simple 1-byte 1-clock RC4 design and its efficient implementation in FPGA coprocessor for secured ethernet communication
Rourab Paul, Sangeet Saha, Jkm Sadique Uz Zaman +3
In the field of cryptography till date the 1-byte in 1-clock is the best known RC4 hardware design [1], while the 1-byte in 3clocks is the best known implementation [2,3]. The desi…