6 citations · 6 across the 12 of their papers we have counts for
12 papers
An evaluation of a microprocessor with two independent hardware execution threads coupled through a shared cache
Madhav P. Desai
We investigate the utility of augmenting a microprocessor with a single execution pipeline by adding a second copy of the execution pipeline in parallel with the existing one. The…
An efficient reverse-lookup table based strategy for solving the synonym and cache coherence problem in virtually indexed, virtually tagged caches
Madhav P. Desai, Aniket Deshmukh
Virtually indexed and virtually tagged (VIVT) caches are an attractive option for micro-processor level-1 caches, because of their fast response time and because they are cheaper t…
Neutron-induced strike: Study of multiple node charge collection in 14nm FinFETs
Nanditha P. Rao, Madhav P. Desai
FinFETs have replaced the conventional bulk CMOS transistors in the sub-20nm technology. One of the key issues to consider is, the vulnerability of FinFET based circuits to multipl…
Neutron induced strike: On the likelihood of multiple bit-flips in logic circuits
Nanditha P. Rao, Madhav P. Desai
High energy particles from cosmic rays or packaging materials can generate a glitch or a current transient (single event transient or SET) in a logic circuit. This SET can eventual…
On Continuous-space Embedding of Discrete-parameter Queueing Systems
Neha Karanjkar, Madhav P. Desai, Shalabh Bhatnagar
Motivated by the problem of discrete-parameter simulation optimization (DPSO) of queueing systems, we consider the problem of embedding the discrete parameter space into a continuo…
Projective cofactor decompositions of Boolean functions and the satisfiability problem
Madhav Desai, Virendra Sule
Given a CNF formula , we present a new algorithm for deciding the satisfiability (SAT) of and computing all solutions of assignments. The algorithm is based on the concept o…
Generalized cofactors and decomposition of Boolean satisfiability problems
Madhav Desai, Virendra Sule
We propose an approach for decomposing Boolean satisfiability problems while extending recent results of \cite{sul2} on solving Boolean systems of equations. Developments in \cite{…
Inner Loop Optimizations in Mapping Single Threaded Programs to Hardware
Madhav Desai
In the context of mapping high-level algorithms to hardware, we consider the basic problem of generating an efficient hardware implementation of a single threaded program, in parti…
Optimization of Discrete-parameter Multiprocessor Systems using a Novel Ergodic Interpolation Technique
Neha V. Karanjkar, Madhav P. Desai
Modern multi-core systems have a large number of design parameters, most of which are discrete-valued, and this number is likely to keep increasing as chip complexity rises. Furthe…
On the likelihood of multiple bit upsets in logic circuits
Nanditha P. Rao, Shahbaz Sarik, Madhav P. Desai
Soft errors have a significant impact on the circuit reliability at nanoscale technologies. At the architectural level, soft errors are commonly modeled by a probabilistic bit-flip…
On Cycles in Random Graphs
Madhav P. Desai
We consider the geometric random (GR) graph on the dimensional torus with the distance measure (). Our main result is an exact characterization of th…
Damped random walks and the characteristic polynomial of the weighted Laplacian on a graph
Madhav Desai, Hariharan Narayanan
For , we define a -damped random walk to be a random walk that is started from a random vertex of a graph and stopped at each step with probability , otherwise…