6 citations · 6 across the 12 of their papers we have counts for
5 papers · 1 filter
An evaluation of a microprocessor with two independent hardware execution threads coupled through a shared cache
Madhav P. Desai
We investigate the utility of augmenting a microprocessor with a single execution pipeline by adding a second copy of the execution pipeline in parallel with the existing one. The…
An efficient reverse-lookup table based strategy for solving the synonym and cache coherence problem in virtually indexed, virtually tagged caches
Madhav P. Desai, Aniket Deshmukh
Virtually indexed and virtually tagged (VIVT) caches are an attractive option for micro-processor level-1 caches, because of their fast response time and because they are cheaper t…
Neutron induced strike: On the likelihood of multiple bit-flips in logic circuits
Nanditha P. Rao, Madhav P. Desai
High energy particles from cosmic rays or packaging materials can generate a glitch or a current transient (single event transient or SET) in a logic circuit. This SET can eventual…
Inner Loop Optimizations in Mapping Single Threaded Programs to Hardware
Madhav Desai
In the context of mapping high-level algorithms to hardware, we consider the basic problem of generating an efficient hardware implementation of a single threaded program, in parti…
On the likelihood of multiple bit upsets in logic circuits
Nanditha P. Rao, Shahbaz Sarik, Madhav P. Desai
Soft errors have a significant impact on the circuit reliability at nanoscale technologies. At the architectural level, soft errors are commonly modeled by a probabilistic bit-flip…