3 citations · 3 across the 2 of their papers we have counts for
3 papers
Pluto: A Benchmark for Evaluating Efficiency of LLM-generated Hardware Code
Manar Abdelatty, Maryam Nouh, Jacob K. Rosenstein +1
Large Language Models (LLMs) are increasingly used to automate hardware design tasks, including the generation of Verilog code. While early benchmarks focus primarily on functional…
MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs
Manar Abdelatty, Jingxiao Ma, Sherief Reda
Large Language Models (LLMs) have been applied to various hardware design tasks, including Verilog code generation, EDA tool scripting, and RTL bug fixing. Despite this extensive e…
ChipXplore: Natural Language Exploration of Hardware Designs and Libraries
Manar Abdelatty, Jacob Rosenstein, Sherief Reda
Hardware design workflows rely on Process Design Kits (PDKs) from different fabrication nodes, each containing standard cell libraries optimized for speed, power, or density. Engin…