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cs.AR2026
CovR: Coverage-Aware Hardware Verification via Reasoning-Guided Reinforcement Learning
Manar Abdelatty, Maryam Nouh, Sherief Reda
Design verification remains one of the most resource-intensive stages of hardware development, often consuming up to 70% of the total design effort. While recent work has explored…
cs.AR2024★ 3 cited
MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs
Manar Abdelatty, Jingxiao Ma, Sherief Reda
Large Language Models (LLMs) have been applied to various hardware design tasks, including Verilog code generation, EDA tool scripting, and RTL bug fixing. Despite this extensive e…