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cs.AR2026
Escaping Flatland: A Placement Flow for Enabling 3D FPGAs
Cong Hao, Andrew B. Kahng, Bodhisatta Pramanik +1
3D field-programmable gate arrays (FPGAs) promise higher performance through vertical integration. However, existing placement tools, largely inherited from 2D frameworks, fail to…
cs.AR2025
OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
Rishov Sarkar, Cong Hao
High-Level Synthesis (HLS) is increasingly popular for hardware design using C/C++ instead of Register-Transfer Level (RTL). To express concurrent hardware behavior in a sequential…
cs.AR2024★ 6 cited
HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
Stefan Abi-Karam, Rishov Sarkar, Allison Seigler +7
Machine learning (ML) techniques have been applied to high-level synthesis (HLS) flows for quality-of-result (QoR) prediction and design space exploration (DSE). Nevertheless, the…