6 citations · 6 across the 6 of their papers we have counts for
6 papers
Escaping Flatland: A Placement Flow for Enabling 3D FPGAs
Cong Hao, Andrew B. Kahng, Bodhisatta Pramanik +1
3D field-programmable gate arrays (FPGAs) promise higher performance through vertical integration. However, existing placement tools, largely inherited from 2D frameworks, fail to…
OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
Rishov Sarkar, Cong Hao
High-Level Synthesis (HLS) is increasingly popular for hardware design using C/C++ instead of Register-Transfer Level (RTL). To express concurrent hardware behavior in a sequential…
Intelligent experiments through real-time AI: Fast Data Processing and Autonomous Detector Control for sPHENIX and future EIC detectors
J. Kvapil, G. Borca-Tasciuc, H. Bossi +30
This R\&D project, initiated by the DOE Nuclear Physics AI-Machine Learning initiative in 2022, leverages AI to address data processing challenges in high-energy nuclear experiment…
HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
Stefan Abi-Karam, Rishov Sarkar, Allison Seigler +7
Machine learning (ML) techniques have been applied to high-level synthesis (HLS) flows for quality-of-result (QoR) prediction and design space exploration (DSE). Nevertheless, the…
LightningSimV2: Faster and Scalable Simulation for High-Level Synthesis via Graph Compilation and Optimization
Rishov Sarkar, Rachel Paul, Cong Hao
High-Level Synthesis (HLS) enables rapid prototyping of complex hardware designs by translating C or C++ code to low-level RTL code. However, the testing and evaluation of HLS desi…
A demonstrator for a real-time AI-FPGA-based triggering system for sPHENIX at RHIC
J. Kvapil, G. Borca-Tasciuc, H. Bossi +28
The RHIC interaction rate at sPHENIX will reach around 3 MHz in pp collisions and requires the detector readout to reject events by a factor of over 200 to fit the DAQ bandwidth of…