9 citations · 11 across the 7 of their papers we have counts for
5 papers · 1 filter
Network Design for Wafer-Scale Systems with Wafer-on-Wafer Hybrid Bonding
Patrick Iff, Tommaso Bonato, Maciej Besta +2
Transformer-based large language models are increasingly constrained by data movement as communication bandwidth drops sharply beyond the chip boundary. Wafer-scale integration usi…
VMXDOTP: A RISC-V Vector ISA Extension for Efficient Microscaling (MX) Format Acceleration
Max Wipfli, Gamze İslamoğlu, Navaneeth Kunhi Purayil +2
Compared to the first generation of deep neural networks, dominated by regular, compute-intensive kernels such as matrix multiplications (MatMuls) and convolutions, modern decoder-…
Evaluating IOMMU-Based Shared Virtual Addressing for RISC-V Embedded Heterogeneous SoCs
Cyril Koenig, Enrico Zelioli, Luca Benini
Embedded heterogeneous systems-on-chip (SoCs) rely on domain-specific hardware accelerators to improve performance and energy efficiency. In particular, programmable multi-core acc…
PlaceIT: Placement-based Inter-Chiplet Interconnect Topologies
Patrick Iff, Benigna Bruggmann, Maciej Besta +2
2.5D integration technology is gaining traction as it copes with the exponentially growing design cost of modern integrated circuits. A crucial part of a 2.5D stacked chip is a low…
RapidChiplet: A Toolchain for Rapid Design Space Exploration of Chiplet Architectures
Patrick Iff, Benigna Bruggmann, Blaise Morel +3
Chiplet architectures are on the rise as they promise to overcome the scaling challenges of monolithic chips. A key component of such architectures is an efficient inter-chiplet in…