21 citations · 24 across the 17 of their papers we have counts for
17 papers
PANDA: An LLM-Enhanced Performance-Driven Analog Design Framework Bridging Design Intent and Layout Generation
Haoyi Zhang, Weijian Fan, Xiaohan Gao +3
Traditional design of analog circuits heavily relies on manual interventions across topology, sizing, and layout, with prior automation addressing stages in isolation. In this work…
FusionCell: Cross-Attentive Fusion of Layout Geometry and Netlist Topology for Standard-Cell Performance Prediction
Haoyi Zhang, Kairong Guo, Bojie Zhang +2
Standard cells form the building blocks of digital circuits, so their delay and power critically influence chip-level performance; yet characterization still relies on slow simulat…
RePart: Efficient Hypergraph Partitioning with Logic Replication Optimization for Multi-FPGA System
Zizhuo Fu, Yifan Zhou, Zhaoxin Lu +4
Multi-FPGA systems (MFS) are widely adopted for VLSI emulation and rapid prototyping. In an MFS, FPGAs connect only to a limited number of neighbors through bandwidth-constrained l…
LaMoSys3.5D: Enabling 3.5D-IC-Based Large Language Model Inference Serving Systems via Hardware/Software Co-Design
Qipan Wang, Zhe Zhang, Shuangchen Li +5
The success of large language models LLMs amplifies the need for highthroughput energyefficient inference at scale. 3DDRAMbased accelerators provide high memory bandwidth and there…
ATMPlace: Analytical Thermo-Mechanical-Aware Placement Framework for 2.5D-IC
Qipan Wang, Tianxiang Zhu, Tianyu Jia +3
Rising demand in AI and automotive applications is accelerating 2.5D IC adoption, with multiple chiplets tightly placed to enable high-speed interconnects and heterogeneous integra…
HeteroSTA: A CPU-GPU Heterogeneous Static Timing Analysis Engine with Holistic Industrial Design Support
Zizheng Guo, Haichuan Liu, Xizhe Shi +5
We introduce in this paper, HeteroSTA, the first CPU-GPU heterogeneous timing analysis engine that efficiently supports: (1) a set of delay calculation models providing versatile a…
Overlay-aware Variation Study of Flip FET and Benchmark with CFET
Wanyue Peng, Haoran Lu, Jingru Jiang +5
In this work, we carried out an overlay-aware variation study on Flip FET (FFET) considering the impact on RC parasitics induced by the lithography misalignment in backside process…
A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-sided Signals
Haoran Lu, Xun Jiang, Yanbang Chu +7
As the conventional scaling of logic devices comes to an end, functional wafer backside and 3D transistor stacking are consensus for next-generation logic technology, offering cons…
AnalogXpert: Automating Analog Topology Synthesis by Incorporating Circuit Design Expertise into Large Language Models
Haoyi Zhang, Shizhao Sun, Yibo Lin +2
Analog circuits are crucial in modern electronic systems, and automating their design has attracted significant research interest. One of major challenges is topology synthesis, wh…
MORE-Stress: Model Order Reduction based Efficient Numerical Algorithm for Thermal Stress Simulation of TSV Arrays in 2.5D/3D IC
Tianxiang Zhu, Qipan Wang, Yibo Lin +2
Thermomechanical stress induced by through-silicon vias (TSVs) plays an important role in the performance and reliability analysis of 2.5D/3D ICs. While the finite element method (…
From Flip FET to Flip 3D Integration (F3D): Maximizing the Scaling Potential of Wafer Both Sides Beyond Conventional 3D Integration
Heng Wu, Haoran Lu, Wanyue Peng +13
In this work, we proposed a new 3D integration technology: the Flip 3D integration (F3D), consisting of the 3D transistor stacking, the 3D dual-sided interconnects, the 3D die-to-d…
Thermal Conductivity of Cubic Silicon Carbide Single Crystals Heavily Doped by Nitrogen
Zifeng Huang, Yunfan Yang, Da Sheng +7
High-purity cubic silicon carbide possesses the second-highest thermal conductivity among large-scale crystals, surpassed only by diamond, making it crucial for practical applicati…
Theseus: Exploring Efficient Wafer-Scale Chip Design for Large Language Models
Jingchen Zhu, Chenhao Xue, Yiqi Chen +13
The emergence of the large language model~(LLM) poses an exponential growth of demand for computation throughput, memory capacity, and communication bandwidth. Such a demand growth…
LayoutCopilot: An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Design
Bingyang Liu, Haoyi Zhang, Xiaohan Gao +5
Analog layout design heavily involves interactive processes between humans and design tools. Electronic Design Automation (EDA) tools for this task are usually designed to use scri…
The Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Models
Lei Chen, Yiqi Chen, Zhufei Chu +36
Within the Electronic Design Automation (EDA) domain, AI-driven solutions have emerged as formidable tools, yet they typically augment rather than redefine existing methodologies.…
EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration
Haoyi Zhang, Jiahao Song, Xiaohan Gao +4
Analog Computing-in-Memory (ACIM) is an emerging architecture to perform efficient AI edge computing. However, current ACIM designs usually have unscalable topology and still heavi…
PDNNet: PDN-Aware GNN-CNN Heterogeneous Network for Dynamic IR Drop Prediction
Yuxiang Zhao, Zhuomin Chai, Xun Jiang +3
IR drop on the power delivery network (PDN) is closely related to PDN's configuration and cell current consumption. As the integrated circuit (IC) design is growing larger, dynamic…