collaborators

7 papers

cond-mat.mes-hall2026

Predictive Structure to Thermal Conductivity Modeling Framework for BEOL Interconnect Stacks in Advanced Technology Nodes Enabled by Extensive Layer Resolved Thermal Measurements

Zifeng Huang, Yiyang Sun, Tianyu Jia +2

The increasing structural complexity of BEOL interconnect stacks in advanced integrated circuits demands a structure-aware thermal conductivity (\k{appa}) modeling framework. Howev…

cond-mat.mes-hall2026

Unveiling the Scaling Potential of Drain Merge through Active (DMtA) in CFETs: Breaking the Super-Via Bottlenecks and Unlocking New PPA Boosters

Jingru Jiang, Haoran Lu, Kairong Guo +11

Drain merge (DM), a super via vertically connecting the common S/D terminals of stacked n/pFETs in Complementary FETs (CFETs), blocks further parasitic optimization and cell scalin…

cond-mat.mtrl-sci2026

A Novel Decoupling Method for Investigating Distinct Domain Evolution in Ferroelectric Film

Keying Sun, Jiajun Qiu, Hao Li +5

Conventional polarization characterization techniques provide only the averaged response of ferroelectric films, limiting the investigation of domain-dependent reliability mechanis…

cond-mat.mtrl-sci2026

High Thermal Conductivity of Back-End-of-Line Compatible Diamond Films

Jinwen Liu, Chufei Cheng, Feifei Tan +6

Back-end-of-line (BEOL) thermal management requires electrically insulating heat-spreading dielectric that can be integrated within thermal budgets below 400 C. Here, we report pol…

cond-mat.mtrl-sci2025

Experimental Observation of Extremely Strong Defect-Phonon Scatterings in Semiconductor Single Crystals

Zifeng Huang, Jianbo Liang, Yuxiang Wang +5

The role of doping in tailoring thermal transport in semiconductors is critical for efficient thermal management in electronic devices. While the effects of doping have been extens…

cond-mat.mes-hall2025

Design Optimization of Flip FET Standard Cells with Dual-sided Pins for Ultimate Scaling

Rui Gui, Haoran Lu, Jiacheng Sun +7

Recently, we proposed a novel transistor architecture for 3D stacked FETs called Flip FET (FFET), featuring N/P transistors back-to-back stacked and dual-sided interconnects. With…

cs.AR2025

A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis

Xun Jiang, Haoran Lu, Yuxuan Zhao +8

As the scaling of semiconductor devices nears its limits, utilizing the back-side space of silicon has emerged as a new trend for future integrated circuits. With intense interest,…