4 papers · 1 filter
SCALE: Self-Supervised Constraint-Aware Layout GEneration for Local P&R DRV Fixing at Advanced Nodes
Chia-Tung Ho, Haoyu Yang, Guanglei Zhou +6
As semiconductor manufacturing advances toward sub-2nm nodes, local place-and-route (P&R) design-rule violation (DRV) fixing is increasingly limited by complex rule interactions, d…
EvoDRC: A Self-Evolving Agentic Framework for Automated DRC Violation Repair
Bing-Yue Wu, Chia-Tung Ho, Haoyu Yang +2
Design rule check (DRC) closure remains a major bottleneck in advanced-node physical design. Although detailed routers are rule-aware, residual design rule violations (DRVs) often…
End-to-End Physical Design Automation Flow for Yield-Optimized Inverse-Designed Large-Scale Electronic-Photonic Integrated Circuits
Hongjian Zhou, Haoyu Yang, Haoxing Ren +2
As AI systems scale to multi-chiplet and wafer-level architectures, the demand for ultra-high bandwidth and system scalability has outpaced the capabilities of electrical interconn…
Pushing the Limits of Inverse Lithography with Generative Reinforcement Learning
Haoyu Yang, Haoxing Ren
Inverse lithography (ILT) is critical for modern semiconductor manufacturing but suffers from highly non-convex objectives that often trap optimization in poor local minima. Genera…