91 citations · 377 across the 12 of their papers we have counts for
6 papers · 1 filter
FracTrain: Fractionally Squeezing Bit Savings Both Temporally and Spatially for Efficient DNN Training
Yonggan Fu, Haoran You, Yang Zhao +5
Recent breakthroughs in deep neural networks (DNNs) have fueled a tremendous demand for intelligent edge devices featuring on-site learning, while the practical realization of such…
SmartExchange: Trading Higher-cost Memory Storage/Access for Lower-cost Computation
Yang Zhao, Xiaohan Chen, Yue Wang +6
We present SmartExchange, an algorithm-hardware co-design framework to trade higher-cost memory storage/access for lower-cost computation, for energy-efficient inference of deep ne…
A New MRAM-based Process In-Memory Accelerator for Efficient Neural Network Training with Floating Point Precision
Hongjie Wang, Yang Zhao, Chaojian Li +2
The excellent performance of modern deep neural networks (DNNs) comes at an often prohibitive training cost, limiting the rapid development of DNN innovations and raising various e…
DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architectures
Yang Zhao, Chaojian Li, Yue Wang +3
The recent breakthroughs in deep neural networks (DNNs) have spurred a tremendously increased demand for DNN accelerators. However, designing DNN accelerators is non-trivial as it…
Fractional Skipping: Towards Finer-Grained Dynamic CNN Inference
Jianghao Shen, Yonggan Fu, Yue Wang +3
While increasingly deep networks are still in general desired for achieving state-of-the-art performance, for many specific inputs a simpler network might already suffice. Existing…
AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs
Pengfei Xu, Xiaofan Zhang, Cong Hao +7
Recent breakthroughs in Deep Neural Networks (DNNs) have fueled a growing demand for DNN chips. However, designing DNN chips is non-trivial because: (1) mainstream DNNs have millio…