Electrostatic Engineering of Nanotube Transistors for Improved Performance

Abstract

With decreasing device dimensions, the performance of carbon nanotube field-effect transistors (CNFETs) is limited by high Off currents except at low drain voltages. We show that an asymmetric design improves the performance, reducing Off currents and extending the usable range of drain voltage. The improvement is most dramatic for ambipolar Schottky-barrier CNFETs. Moreover, this approach allows a single device to exhibit equally good performance as an n- or p-type transistor, by changing only the sign of the drain voltage. Even for CNFETs having ohmic contacts, an asymmetric design can greatly improve the performance for small-bandgap nanotubes.

4 pages, 5 figures

References in corpus (3)

• Carbon Nanotubes as Schottky Barrier Transistors
• Drain Voltage Scaling in Carbon Nanotube Transistors
• Lateral scaling in carbon nanotube field-effect transistors

Cited by in corpus (12)

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• Unexpected Scaling of the Performance of Carbon Nanotube Transistors
• Electronic Devices Based on Purified Carbon Nanotubes Grown By High Pressure Decomposition of Carbon Monoxide
• High-Performance, Hysteresis-Free Carbon Nanotube FETs via Directed Assembly
• Photo-gating Carbon Nanotube Transistors
• Local pressure-induced metallization of a semiconducting carbon nanotube in a crossed junction
• Predicted Performance Advantages of Carbon Nanotube Transistors with Doped Nanotubes as Source/Drain
• A Computational Study of Vertical Partial Gate Carbon Nanotube FETs
• Electron transport in armchair single-wall carbon nanotubes
• Modulating transmission properties of nanoscale transistors by dipole effects near contacts