Two-dimensional Indium Oxide at the Epitaxial Graphene/SiC Interface: Synthesis, Structure, Properties, and Devices

Abstract

High-quality two-dimensional (2D) dielectrics are crucial for fabricating 2D/3D hybrid vertical electronic devices such as metal-oxide-semiconductor (MOS) based Schottky diodes and hot electron transistors, the production of which is constrained by the scarcity of bulk layered wide bandgap semiconductors. In this research, we present the synthesis of a new 2D dielectric, monolayer InO2, which differs in stoichiometry from its bulk form, over a large area (>300 um2) by intercalating at the epitaxial graphene (EG)/SiC interface. By adjusting the lateral size of graphene through optical lithography prior to the intercalation, we tune the thickness of InO2 where predominantly (~85%) monolayer InO2 is formed. The preference for monolayer formation of InO2 is explained using ReaxFF reactive molecular dynamics and density functional theory (DFT) calculations. Additionally, the band gap of InO2 is calculated to be 4.1 eV, differing from its bulk form (2.7 eV). Furthermore, MOS-based Schottky diode measurements on InO2 intercalated EG/n-SiC demonstrate that the EG/n-SiC junction transforms from ohmic to a Schottky junction upon intercalation, with a barrier height of 0.87 eV and a rectification ratio of ~10^5. These findings introduce a new addition to the 2D dielectric family, showing significant potential for monolayer InO2 to be used as a barrier in vertical electronic devices.

References in corpus (7)

• A real-space grid implementation of the Projector Augmented Wave method
• Localized atomic basis set in the projector augmented wave method
• Scaled indium oxide transistors fabricated using atomic layer deposition
• Semiconductor to metal transition in two-dimensional gold and its van der Waals heterostack with graphene
• Bulk and surface characterization of In${}_2$O${}_3$(001) single crystals
• A library of ab initio Raman spectra for automated identification of 2D materials
• Bilayer Insulator Tunnel Barriers for Graphene-Based Vertical Hot-electron Transistors